LC87F40C8A Datasheet, PDF (16/26 Pages) Sanyo Semicon Device – Internal 128K-byte FROM (ROM/CGROM), 2048 byte RAM, 1024-byte CGRAM, and 704×10-bit CRT Display RAM 8-bit 1-chip Microcontroller

LC87F40C8A
Serial I/O Characteristics at Ta = -10°C to +70°C, VSS1 = VSS2 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter
Period
Symbol
tSCK(1)
Pin/
Remarks
SCK0(P12)
Conditions
See Fig. 5.
VDD[V]
min
2
Low level
pulse width
High level
pulse width
Period
Low level
pulse width
High level
pulse width
Data setup time
Data hold time
tSCKL(1)
tSCKH(1)
tSCKHA(1a)
tSCKHA(1b)
tSCK(2)
tSCKL(2)
tSCKH(2)
tSCKHA(2a)
tSCKHA(2b)
tsDI(1)
thDI(1)
SCK0(P12)
SI0(P11),
SB0(P11)
• Continuous data transmission/
reception mode
• OSD inactive
• See Fig. 5.
• (Note4-1-2)
• Continuous data transmission/
reception mode
• OSD active
• See Fig. 5.
• (Note4-1-2)
• CMOS output selected
• See Fig. 5.
• Continuous data transmission/
reception mode
• OSD inactive
• See Fig. 5.
• Continuous data transmission/
reception mode
• OSD active
• See Fig. 5.
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 5.
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
1
1
4
6
4/3
tSCKH(2)
+2tCYC
tSCKH(2)
+2tCYC
0.03
0.03
Specification
typ
max
unit
tCYC
1/2
tSCK
1/2
tSCKH(2)
+(10/3)
tCYC
tSCKH(2)
+(16/3)
tCYC
tCYC
Output
delay time
tdD0(1)
tdD0(2)
tdD0(3)
SO0(P10),
SB0(P11),
• Continuous data transmission/
reception mode
• (Note4-1-3)
• Synchronous 8-bit mode
• (Note4-1-3)
(Note4-1-3)
4.5 to 5.5
(1/3)tCYC
+0.05
µs
1tCYC
+0.05
(1/3)tCYC
+0.05
Note4-1-1: This standard value is a theory value. Be sure to ensure the margin according to busy condition.
Note4-1-2: When using the serial clock in continuous data transmission/reception mode, the time to the first falling
edge of the serial clock after it sets SIORUN in “H” state is more extended than tSCLKHA.
Note4-1-3: It is defined for the falling edge of SIOCLK. In open drain output, it is defined as the time to start the output
change. See Fig. 5.
No.A0139-16/26