LC875032A Datasheet, PDF (16/25 Pages) Sanyo Semicon Device – 8-Bit Single Chip Microcontroller with 32/24/16K-Byte EPROM and 640-Byte RAM On Chip

LC875032A/24A/16A
5. Parallel Input/Output Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V
Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format.
Please refer to figures 8 and 9 for parallel output timing waveforms.
Parameter
Symbol
Pins
Conditions
Write cycle,
Read cycle
Address set-up
time
tC(1)
tsA(1)
tsA(2)
• WR (PA3), PB0-PB7
• RD (PA4), PC0-PC7
RD (PA4), PC0-PC7
From address set-up
until control signal
changes
Address hold time thA(1)
thA(2)
RS set-up tie
tsRS(1)
tsRS(2)
tsRS(3)
RD (PA4), PC0-PC7
WR (PA3), PC0-PC7
WR (PA3), RS(PA5),
CS (PAX)
RD (PA4), RS(PA5)
RD (PA4), RS(PA5)
From change of RD
until address change
From change of WR
until address change
From change of RS,
CS until change in
WR
from change of RS
until change in RD
CS
set-up time
RS
hold time
CS
hold time
WR
’H’ pulse width
tsCS(1)
tsCS(2)
thRS(1)
thRS(2)
thRS(3)
thCS(1)
thCS(2)
tWRH(1)
tWRH(2)
RD (PA4), CS (PAX)
WR (PA3), CS (PAX)
WR (PA3), RS(PA5)
RD (PA4), RS(PA5),
CS (PAX)
RD (PA4), RS(PA5),
CS (PAX)
RD (PA4), RS(PA5)
WR (PA3), RS(PA5)
WR (PA3)
From change in CS
until change in RD
From change in CS
until change in WR
From change in WR
until change in RS
From change in RD
until change in RS,
CS
From change in RD
until change in CS
From change in WR
until change in CS
WR (PA3)
WR
’L’ pulse width
tWRL(1)
tWRL(2)
WR (PA3)
WR (PA3)
Ratings
VDD[V] min.
typ.
2.5 - 6.0
1
2.5 - 6.0
2.5 - 6.0
2.5 - 6.0
1/3tCYC
-30ns
2/3tCYC
-30ns
1/6tCYC
2.5 - 6.0
5
2.5 - 6.0 1/6tCYC
-15ns
2.5 - 6.0
2.5 - 6.0
2.5 - 6.0
1/6tCYC
-15ns
1/3tCYC
-15ns
1/3tCYC
-15ns
2.5 - 6.0 2/3tCYC
-15ns
2.5 - 6.0
0
2.5 - 6.0 1/6tCYC
2.5 - 6.0
0
2.5 - 6.0 1/6tCYC
2.5 - 6.0
0
2.5 - 6.0
2.5 - 6.0
2.5 - 6.0
2.5 - 6.0
1/6tCYC
-5ns
2/3tCYC
-5ns
1/6tCYC
-5ns
1/3tCYC
-5ns
1/6
tCYC
2/3
tCYC
1/6
tCYC
1/3
tCYC
max.
unit
tCYC
tCYC
& ns
ns
tCYC
& ns
ns
tCYC
& ns
ns
tCYC
& ns
ns
tCYC
& ns
(Continued)
No.6713-16/25