LC87F7LC8A Datasheet, PDF (13/25 Pages) Sanyo Semicon Device – CMOS IC FROM 128K byte, RAM 4096 byte on-chip 8-bit 1-chip Microcontroller

LC87F7LC8A
Allowable Operating Conditions at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Operating
supply voltage
(Note 2-1)
Symbol
VDD(1)
VDD(2)
VDD(3)
Pin/Remarks
Conditions
VDD1=VDD2=VDD3
0.237μs≤tCYC≤200μs
0.356μs≤tCYC≤200μs
0.712μs≤tCYC≤200μs
VDD[V]
Specification
min
typ
max
unit
3.0
5.5
2.5
5.5
2.2
5.5
Memory
sustaining
VHD
VDD1
RAM and register contents
sustained in HOLD mode.
2.0
5.5
supply voltage
High level input
voltage
VIH(1)
Ports 0, 3, 8
Ports A, B, C, D, E, F
Port L
Output disabled
2.2 to 5.5
0.3VDD
+0.7
VDD
VIH(2)
Port 1
Ports 71 to 73
P70 port input/
• Output disabled
• When INT1VTSL=0
(P71 only)
2.2 to 5.5
0.3VDD
+0.7
VDD
interrupt side
VIH(3)
P71 interrupt side
• Output disabled
• When INT1VTSL=1
2.2 to 5.5 0.85VDD
VDD
VIH(4)
VIH(5)
P87 small signal
input side
P70 watchdog timer
side
Output disabled
Output disabled
2.2 to 5.5
2.2 to 5.5
0.75VDD
0.9VDD
VDD
V
VDD
VIH(6)
XT1, XT2, CF1, RES
2.2 to 5.5 0.75VDD
VDD
Low level input
voltage
VIL(1)
Ports 0, 3, 8
Output disabled
Ports A, B, C, D, E, F
4.0 to 5.5
VSS
0.15VDD
+0.4
VIL(2)
Port L
Port 1
Ports 71 to 73
• Output disabled
• When INT1VTSL=0
2.2 to 4.0
4.0 to 5.5
VSS
VSS
0.2VDD
0.1VDD
+0.4
P70 port input/
interrupt side
(P71 only)
2.2 to 4.0
VSS
0.2VDD
VIL(3)
P71 interrupt side
• Output disabled
• When INT1VTSL=1
2.2 to 5.5
VSS
0.45VDD
VIL(4)
P87 small signal
input side
Output disabled
2.2 to 5.5
VSS
0.25VDD
VIL(5)
P70 watchdog timer
side
Output disabled
2.2 to 5.5
VSS
0.8VDD
-1.0
Instruction cycle
time
(Note 2-2)
VIL(6)
tCYC
XT1, XT2, CF1, RES
2.2 to 5.5
3.0 to 5.5
2.5 to 5.5
2.2 to 5.5
VSS
0.237
0.356
0.712
0.25VDD
200
200 μs
200
External system FEXCF(1) CF1
• CF2 pin open
3.0 to 5.5
0.1
12
clock frequency
• System clock frequency
2.5 to 5.5
0.1
8
division ratio=1/1
• External system clock
duty=50±5%
2.2 to 5.5
0.1
4
MHz
• CF2 pin open
3.0 to 5.5
0.2
24.4
• System clock frequency
2.5 to 5.5
0.2
16
division ratio=1/2
2.2 to 5.5
0.2
8
Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a
division ratio of 1/2.
Continued on next page.
No.A0835-13/25