LB11870 Datasheet, PDF (13/14 Pages) Sanyo Semicon Device – Three-Phase Brushless Motor Driver for Polygonal Mirror Motors

LB11870
7. Hall Input Signals
Signals with an amplitude in excess of the hysteresis (42 mV maximum) must be provided as the Hall input signals.
However, an amplitude of over 100 mV is desirable to minimize the influence of noise. If the output waveforms are
disturbed (at phase switching) due to noise on the Hall inputs, insert capacitors across these inputs.
8. FG Input Signal
Normally, one phase of the Hall signals is input as the FG signal. If noise is a problem the input must be filtered with
either a capacitor or an RC filter circuit. Although it is also possible to remove FG signal noise by inserting a
capacitor between the FGFIL pin and ground, the IC may not be able to operate correctly if this signal is damped
excessively. If this capacitor is used, its value must be less than about 2200 pF. If the location of this capacitor's
ground lead is inappropriate, it may, inversely, make noise problems even more likely to occur. Thus the ground lead
location must be chosen carefully.
9. Rotor Constraint Protection Circuit
This IC provides a rotor constraint protection circuit to protect the IC itself and the motor when the motor is
constrained. If the LD output is high (unlocked) for over a certain fixed period with the IC in the start state, the low
side transistor will be turned off. The time constant is determined by the capacitor connected to the CSD pin.
<time constant (in seconds)> ^.=. 120 × C (µF)
If a 0.068 µF capacitor is used, the protection time will be about 8 seconds. The set time must be selected to have an
adequate margin with respect to the motor startup time. This protection circuit will not operate during deceleration
when the clock frequency is switched. To clear the rotor constraint protection state, the IC must be set to the stopped
state or the power must be turned off and reapplied.
Since the CSD pin also functions as the initial reset pulse generation pin at startup, the logic circuit will go to the
reset state and the IC will not be able to function if this pin is connected to ground. Therefore, both a 220 kΩ resistor
and a 4700 pF capacitor must be inserted between this pin and ground if the rotor constraint protection circuit is not
used.
10. Phase Lock Signal
(1) Phase lock range
Since this IC does not include a counter or similar functionality in the speed control system, the speed error range
in the phase locked state cannot be determined solely by IC characteristics. (This is because the acceleration of the
changes in the FG frequency influences the range.) When it is necessary to stipulate this characteristic for the
motor, the designer must determine this by measuring the actual motor state. Since speed errors occur easily in
states where the FG acceleration is large, it is thought that the speed errors will be the largest during lock pull-in at
startup and when unlocked due to switching clock frequencies.
(2) Masking function for the phase lock state signal
A stable lock signal can be provided by masking the short-term low-level signals due to hunting during lock pull-
in. However, this results in the lock state signal output being delayed by the masking time.
The masking time is determined by the capacitor inserted between the CLD pin and ground.
<masking time (seconds)> ^.=. 0.9 × C (µF)
When a 0.1 µF capacitor is used, the masking time will be about 90 ms. In cases where complete masking is required,
a masking time with fully adequate margin must be used. If no masking is required, leave the CLD pin open.
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