LB11870 Datasheet, PDF (12/14 Pages) Sanyo Semicon Device – Three-Phase Brushless Motor Driver for Polygonal Mirror Motors

LB11870
Overview of the LB11870
1. Speed Control Circuit
This IC adopts a PLL speed control technique and provides stable motor operation with high precision and low jitter.
This PLL circuit compares the phase error at the edges of the CLK signal (falling edges) and FG signal (falling edges
on the FGIN+ and FGS signals), and the IC uses the detected error to control motor speed.
During this control operation, the FG servo frequency will be the same as the CLK frequency.
f_FG (servo) = f_CLK
2. Output Drive Circuit
To minimize power loss in the output circuits, this IC adopts a direct PWM drive technique. The output transistors are
always saturated when on, and the IC adjusts the motor drive output by changing the output on duty. The low side
output transistor is used for the output PWM switching.
Both the high and low side output diodes are integrated in the IC. However, if reverse torque control mode is selected
for use during deceleration, or if a large output current is used and problems occur (such as incorrect operation or
waveform disruption due to low side kickback), a Schottky diode should be inserted between OUT and ground. Also,
if it is necessary to reduce IC heating during steady-state (constant speed) operation, it may be effective to insert a
Schottky diode between V_CC and OUT. (This is effective because the load associated with the regenerative current
during PWM switching is born not by the on-chip diode but by the external diode.)
3. Current Limiter Circuit
The current limiter circuit limits the peak level of the current to a level determined by I = VRF/Rf (where VRF =
0.5 V (typical) and Rf is the value of the current detection resistor). The current limiter operates by reducing the
output on duty to suppress the current.
The current limiter circuit detects the reverse recovery current of the diode due to PWM operation. To assure that the
current limiting function does not malfunction, its operation has a delay of about 2 µs. If the motor coils have a low
resistance or a low inductance, current fluctuations at startup (when there is no reactive power in the motor) will be
rapid. The delay in this circuit means that at such times the current limiter circuit may operate at a point well above
the set current. Designers must take this increase in the current due to the delay into account when setting the current
limiter value.
4. Power Saving Circuit
This IC goes into a power saving state that reduces the current drain in the stop state. The power saving state is
implemented by removing the bias current from most of the circuits in the IC. However, the 5 V regulator output is
provided in the power saving state.
5. Reference Clock
Care must be taken to assure that no chattering or other noise is present on the externally input clock signal. Although
the input circuit does have hysteresis, if problems do occur, the noise must be excluded with a capacitor.
If the IC is set to the start state when the reference clock signal is not present, if the rotor constraint protection circuit
is used, the motor will turn somewhat and then motor drive will be shut off. However, if the rotor constraint
protection circuit is not used, and furthermore reverse torque control mode is selected for deceleration, the motor will
be driven at ever increasing speed in the reverse direction. (This is because the rotor constraint protection circuit
oscillator signal is used for clock cutoff protection.) Applications must implement a workaround for this problem if
there is any possibility whatsoever for it to occur.
6. Notes on the PWM Frequency
The PWM frequency is determined by the value of the capacitor C (in F) connected to the PWM pin.
f_PWM ^.=. 1 / (43000 × C)
If a 680 pF capacitor is used, the circuit will oscillate at about 34 kHz. If the PWM frequency is too low, the motor
will emit switching noise, and if it is too high, the power loss in the output will be excessive. A PWM frequency in
the range 15 to 50 kHz is desirable. To minimize the influence of the output on this circuit, the ground lead of this
capacitor should be connected as close as possible to the IC control system ground (the GND1 pin).
No. 7256 -12/14