LC8766C8A Datasheet, PDF (11/23 Pages) Sanyo Semicon Device – 8-Bit Single Chip Microcontroller

LC8766C8A/B2A/96A
2. Recommended Operating Range at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter Symbol
Pins
Conditions
Ratings
unit
VDD[V] min. typ. max.
Operating
VDD(1) VDD1=VDD2=VDD3
supply voltage
=VDD4
0.294µs ≤ Tcyc
≤ 200µs
4.5
6.0
V
range
Hold voltage VHD
VDD1
RAM and the
2.0
6.0
register data are
kept in HOLD
mode.
Pull-down
VP
VP
4.5–6.0 -35
VDD
voltage
Input high
VIH(1) •Port 0,3: CMOS output Output disable
4.5–6.0 0.3VDD
VDD
voltage
option
+0.7
•Port 8
VIH(2) Port 0,3: N-ch open drain Output disable
4.5–6.0 0.3VDD
13.5
output
+0.7
VIH(3) •Port 1
Output disable
4.5–6.0 0.3VDD
VDD
•Port71,72,73
+0.7
•P70 port input/interrupt
VIH(4) S16 to S51
Output P-channel 4.5–6.0 0.3VDD
VDD
Tr. OFF
+1.0
VIH(5) P70 Weak signal input Output disable
4.5–6.0 0.75VDD
VDD
VIH(6) Port 70
Output disable
4.5–6.0 0.9VDD
VDD
Watchdog timer
VIH(7) XT1, XT2, CF1, RES
4.5–6.0 0.75VDD
VDD
Input low
voltage
VIL(1)
VIL(2)
VIL(3)
VIL(4)
VIL(5)
VIL(6)
VIL(7)
Operation
tCYC
cycle time
External system fEXCF(1)
clock
frequency
•Port 0,3: CMOS output Output disable
option
•Port 8
Port 0,3: N-ch open drain Output disable
output
•Port 1
Output disable
•Port 71,72,73
•P70 port input/interrupt
S16 to S51
Output P-channel
Tr. OFF
Port 87 weak signal input Output disabled
Port 70
Output disabled
Watchdog timer
XT1,XT2,CF1, RES
CF1
•CF2 open circuit
•system clock
divider set to 1/1
•external clock
DUTY = 50±50%
•CF2 open circuit
•system clock
divider set to 1/2
Continued
4.5–6.0
4.5–6.0
4.5–6.0
4.5–6.0
4.5–6.0
4.5–6.0
4.5–6.0
4.5–6.0
4.5–6.0
4.5–6.0
VSS
VSS
VSS
-35
VSS
VSS
VSS
0.294
0.1
0.2
0.15VDD
+0.4
0.15VDD
+0.4
0.1VDD
+0.4
0.2VDD
0.25VDD
0.8VDD
-1.0
0.25VDD
200 µs
10 MHz
20
No.6718-11/23