LC8220 Datasheet, PDF (11/13 Pages) Sanyo Semicon Device – JPEG Still Color Image Compression/Decompression LSI

Control Bus Interface Timing
Control Bus Read Cycle
LC8220
Control Bus Register Read Cycle (type 1)
Control Bus Register Read Cycle (type 2)
Item
t1
Read signal assert setup time (referenced to CLK)
t2
Read signal assert hold time (referenced to CLK)
t3
Chip select stabilization time (referenced to the read signal)
t4
Chip select hold time (referenced to the read signal)
t5
Address stabilization time (referenced to the read signal)
t6
Address hold time (referenced to the read signal)
t7
Ready signal response delay time (referenced to the read signal)
t8
Ready signal release delay time (referenced to the read signal)
t9
Read signal negate setup time (referenced to CLK)
t10
Read signal negate hold time (referenced to CLK)
t11
Data output delay time (referenced to the ready signal)
t12
Data output hold time (referenced to the read signal)
T
Clock period
Minimum
10
15
10
15
0
5
12
15
60
Maximum
Unit
ns
ns
ns
ns
ns
ns
T + t1 + 24
ns
t9 + 30
ns
ns
ns
0
ns
t9 + 30
ns
ns
No. 4909-11/13