K4S643232E-TI Datasheet, PDF (9/12 Pages) Samsung semiconductor – 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL

K4S643232E-TI/P
CMOS SDRAM
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Symbol
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
Version
-60
-70
12
14
18
20
18
20
42
49
100
60
70
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Unit
ns
ns
ns
ns
us
ns
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
Symbol
CLK cycle time
CAS Latency=3
tCC
CAS Latency=2
CLK to valid
output delay
CAS Latency=3
tSAC
CAS Latency=2
Output data hold time
tOH
CLK high pulse width
CAS Latency=3
tCH
CAS Latency=2
CLK low
pulse width
CAS Latency=3
tCL
CAS Latency=2
Input setup time
CAS Latency=3
tSS
CAS Latency=2
Input hold time
tSH
CLK to output in Low-Z
tSLZ
CLK to output
in Hi-Z
CAS latency=3
tSHZ
CAS latency=2
-60
Min
Max
6
1000
10
-
5.5
-
6
2
-
2.5
-
3
-
2.5
-
3
-
1.5
-
2.5
-
1
-
1
-
-
5.5
-
6
-70
Min
Max
7
1000
10
-
5.5
-
6
2
-
3
-
3
-
3
-
3
-
1.75
-
2.5
-
1
-
1
-
-
5.5
-
6
Note : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Unit Note
ns
1
ns
1, 2
ns
2
ns
3
ns
3
ns
3
ns
3
ns
2
ns
-
Rev. 1.2 (Oct. 2001)
-9-