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K4S643232E-TI Datasheet, PDF (7/12 Pages) Samsung semiconductor – 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL | |||
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K4S643232E-TI/P
CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = -45oC to +85oC, VIH(min)/VIL(max)=2.0V/0.8V)
Parameter
Operating Current
(One Bank Active)
Symbol
Test Condition
ICC1
Burst Length =1
tRC ⥠tRC(min), tCC ⥠tCC(min), Io = 0mA
CAS
Latency
3
2
Speed
-60
-70
170
155
150
150
Precharge Standby Current in ICC2P
CKE ⤠VIL(max), tCC = 15ns
3
power-down mode
ICC2PS
CKE & CLK ⤠VIL(max), tCC = â
2
Precharge Standby Current
ICC2N
CKE ⥠VIH(min), CS ⥠VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
20
in non power-down mode
ICC2NS
CKE ⥠VIH(min), CLK ⤠VIL(max), tCC = â
Input signals are stable
10
Active Standby Current
ICC3P
CKE ⤠VIL(max), tCC = 15ns
7
in power-down mode
ICC3PS
CKE ⤠VIL(max), tCC = â
5
Active Standby Current
ICC3N
CKE ⥠VIH(min), CS ⥠VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
55
in non power-down mode
(One Bank Active)
ICC3NS
CKE ⥠VIH(min), CLK ⤠VIL(max), tCC = â
Input signals are stable
40
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
ICC4
Io = 0 mA, Page Burst
All bank Activated, tCCD = tCCD(min)
ICC5
tRC ⥠tRC(min)
ICC6
CKE ⤠0.2V
3
180
170
2
150
150
3
185
165
2
160
160
3
450
Unit Note
mA 2
mA
mA
mA
mA
mA 2
mA 3
mA 4
uA 5
Notes : 1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.
2. Measured with outputs open.
3. Refresh period is 64ms.
4. K4S643232E-TI**
5. K4S643232E-TP**
Rev. 1.2 (Oct. 2001)
-7-
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