K8S6815ETD Datasheet, PDF (8/48 Pages) Samsung semiconductor – 64Mb D-die SLC NOR FLASH

K8S6815ET(B)D
Rev. 1.2
datasheet NOR FLASH MEMORY
7.0 PRODUCT INTRODUCTION
The K8S6815E is a 64Mbit (67,108,364 bits) NOR-type Burst Flash memory. The device features 1.8V single voltage power supply operating within the
range of 1.7V to 1.95V. The device is programmed by using the Channel Hot Electron (CHE) injection mechanism which is used to program EPROMs.
The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To provide highly flexible erase and program capability, the device
adapts a block memory architecture that divides its memory array into 135 blocks (32-Kword x 127, 4-Kword x 8). Programming is done in units of 16
bits (Word). All bits of data in one or multiple blocks can be erased when the device executes the erase operation. To prevent the device from accidental
erasing or over-writing the programmed data, 135 memory blocks can be hardware protected. Regarding read access time, at 54MHz, the K8S6815E
provides a burst access of 14.5ns with initial access times of 70ns at 30pF. At 66MHz, the K8S6815E provides a burst access of 11ns with initial access
times of 70ns at 30pF. At 83MHz, the K8S6815E provides a burst access of 9ns with initial access times of 70ns at 30pF. At 108MHz, the K8S6815E
provides a burst access of 9ns with initial access times of 70ns at 30pF. The command set of K8S6815E is compatible with standard Flash devices. The
device uses Chip Enable (CE), Write Enable (WE), Address Valid(AVD) and Output Enable (OE) to control asynchronous read and write operation. For
burst operations, the device additionally requires Ready (RDY) and Clock (CLK). Device operations are executed by selective command codes. The
command codes to be combined with addresses and data are sequentially written to the command registers using microprocessor write timing. The
command codes serve as inputs to an internal state machine which controls the program/erase circuitry. Register contents also internally latch
addresses and data necessary to execute the program and erase operations. The K8S6815E is implemented with Internal Program/Erase Routines to
execute the program/erase operations. The Internal Program/Erase Routines are invoked by program/erase command sequences. The Internal Pro-
gram Routine automatically programs and verifies data at specified address. The Internal Erase Routine automatically pre-programs the memory cell
which is not programmed and then executes the erase operation. The K8S6815E has means to indicate the status of completion of program/erase oper-
ations. The status can be indicated via Data polling of DQ7, or the Toggle bit (DQ6). Once the operations have been completed, the device automatically
resets itself to the read mode. The device requires 24mA burst read current and 15mA for program/erase operations.
[Table 5] Device Bus Operations
Operation
Asynchronous Read Operation
Write
Standby
Hardware Reset
Load Initial Burst Address
Burst Read Operation
Terminate Burst Read Cycle via CE
Terminate Burst Read Cycle via RESET
Terminate Current Burst Read Cycle and Start
New Burst Read Cycle
NOTE :
L=VIL (Low), H=VIH (High), X=Don’t Care.
CE
OE
WE
A16-21
A/DQ0-15 RESET
CLK
AVD
L
L
H
Add In Add In/DOUT
H
L
L
H
L
Add In Add In / DIN
H
L
H
X
X
X
High-Z
H
X
X
X
X
X
X
High-Z
L
X
X
L
H
H
Add In
Add In
H
L
L
H
X
Burst
DOUT
H
H
H
X
X
X
High-Z
H
X
X
X
X
X
X
High-Z
L
X
X
L
H
H
Add In
Add In
H
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