K8S6815ETD Datasheet, PDF (17/48 Pages) Samsung semiconductor – 64Mb D-die SLC NOR FLASH

K8S6815ET(B)D
Rev. 1.2
datasheet NOR FLASH MEMORY
9.18 Program Suspend / Resume
The device provides the Program Suspend/Resume mode. This mode is used to enable Data Read by suspending the Program operation. The device
accepts a Program Suspend command in Program mode(including Program operations performed during Erase Suspend) but other commands are
ignored. After input of the Program Suspend command, 10us is needed to enter the Program Suspend Read mode. Therefore system must wait for
10us(recovery time) to read the data from the bank which include the block being programmed. Otherwise, system can read the data immediately from a
bank which don't include block being programmed without recovery time(max. 10us) after Program Suspend command. Like an Erase Suspend mode,
the device can be returned to Program mode by using a Program Resume command. In program suspend followed by resume operation, min. 200ns is
needed for checking the busy status.
While program operation can be suspended and resumed multiple times, a minimum 30us is required from resume to the next suspend.
9.19 Read While Write Operation
The device is capable of reading data from one bank while writing in the other banks. This is so called the Read While Write operation. An erase operation
may also be suspended to read from or program to another location within the same bank(except the block being erased). The Read While Write opera-
tion is prohibited during the chip erase operation. Figure 17 shows how read and write cycles may be initiated for simultaneous operation with zero
latency. Refer to the DC Characteristics table for read-while-write current specifications.
9.20 OTP Block Region
The OTP Block feature provides a 256-word Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN).
The OTP Block is customer lockable and shipped with itself unlocked, allowing customers to utilize the that block in any manner they choose. The cus-
tomer-lockable OTP Block has the Protection Verify Bit (DQ0) set to a "0" for Unlocked state or a "1" for Locked state.
The system accesses the OTP Block through a command sequence (see "Enter OTP Block / Exit OTP Block Command sequence" at Table 6). After the
system has written the "Enter OTP Block" Command sequence, it may read the OTP Block by using the address (3FFF00h~3FFFFFh, in top boot
device),(000000h~0000FFh, in bottom boot device)normally and may check the Protection Verify Bit (DQ0) by using the "Autoselect Block Protection Ver-
ify" Command sequence with OTP Block address. This mode of operation continues until the system issues the "Exit OTP Block" Command sequence, a
hardware reset or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to main
blocks. Note that the Accelerated function and unlock bypass modes are not available when the OTP Block is enabled.
Customer Lockable
In a Customer lockable device, The OTP Block is one-time programmable and can be locked only once. Note that the Accelerated programming and
Unlock bypass functions are not available when programming the OTP Block. Locking operation to the OTP Block is started by writing the "Enter OTP
Block" Command sequence, and then the "Block Protection" Command sequence (Table 6) with an OTP Block address. Hardware reset terminates Lock-
ing operation, and then makes exiting from OTP Block. The Locking operation has to be above 100us. (After 3rd cycle of protection command invoked, at
least 100us wait time is required.) "Exit OTP Block" command sequence and Hardware reset makes locking operation finished and then exiting from OTP
Block after 30us.
The OTP Block Lock operation must be used with caution since, once locked, there is no procedure available for unlocking and none of the
bits in the OTP Block space can be modified in any way.
Suspend and resume operation are not supported during OTP protect, nor is OTP protect supported during any suspend operations.
Write Pulse “Glitch” Protection
Noise pulses of less than 5ns (typical) on OE, CE, AVD or WE do not initiate a write cycle.
9.21 Low VCC Write Inhibit
To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for Vcc less than VLKO. If the Vcc < VLKO (Lock-Out
Voltage), the command register and all internal program/erase circuits are disabled. Under this condition the device will reset itself to the read mode.Sub-
sequent writes will be ignored until the Vcc level is greater than VLKO. It is the user’s responsibility to ensure that the control pins are logically correct to
prevent unintentional writes when Vcc is above VLKO.
9.22 Logical Inhibit
Write cycles are inhibited by holding any one of OE = VIL , CE = VIH or WE = VIH. To initiate a write cycle, CE and WE must be a logical zero while OE is
a logical one.
9.23 Power-up Protection
To avoid initiation of a write cycle during VCC power-up, RESET low must be asserted during Power-up. After RESET goes high. the device is reset to the
read mode.
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