S6C0671 Datasheet, PDF (7/29 Pages) Samsung semiconductor – 8 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER

8 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
S6C0671
PIN DESCRIPTIONS
Symbol
VDD1
VDD2
VSS1
VSS2
Y1 – Y384
D0<0:7>
- D5<0:7>
SHL
DIO1
DIO2
DATPOL1
DATPOL2
POL
CLK2
CLK1
VGMA1
–
VGMA18
TEST
Pin Name
Logic power supply
Driver power supply
Logic ground
Driver ground
Driver outputs
Display data input
Shift direction control
input
Start pulse input/output
Start pulse input/output
Data inversion input
Polarity input
Shift clock input
Latch input
Gamma corrected power
supplies
Test input
Description
2.7 - 3.6 V
8.0 - 15.0 V
Ground (0 V)
Ground (0 V)
The D/A converted 256 gray-scale analog voltage is output.
The display data is input with a width of 48 bits,
gray-scale data (8 bits) by 6 dots (R,G,B) DX0: LSB, DX7: MSB
This pin controls the direction of shift register in cascade connection.
The shift direction of the shift registers is as follows.
SHL = H: DIO1 input, Y1 → Y384, DIO2 output
SHL = L: DIO2 input, Y384 → Y1, DIO1 output
SHL = H: Used as the start pulse input pin.
SHL = L: Used as the start pulse output pin.
SHL = H: Used as the start pulse output pin.
SHL = L: Used as the start pulse input pin.
DATPOL1,2 = L: Display data is not inverted
DATPOL1 = H: Display data of D0<0:7> - D2<0:7> is inverted
DATPOL2 = H: Display data of D3<0:7> - D5<0:7> is inverted
POL = H: The reference voltage for odd number outputs are VGMA10 –
VGMA18 and those for even number outputs are VGMA1 – VGMA9.
POL = L: The reference voltage for odd number outputs are VGMA1 –
VGMA9 and those for even number outputs are VGMA10 – VGMA18.
Refer to the shift register's shift clock input. the display data is loaded to
the data register at the rising edge of CLK2.
Latches the contents of the data register at rising edge and transfers
them to the D/A converter. Also, after CLK1 input, clears the internal
shift register contents. After 1 pulse input on start, operates normally.
CLK1 input timing refers to the "Relationships between CLK1 start pulse
(DIO1, DIO2) and blanking period" of the switching characteristic
waveform. Outputs the G/S data at falling edge.
Input the gamma corrected power supplies from external source.
VDD2 > VGMA1 > VGMA2 > …… > VGMA17 > VGMA18 > VSS2
Keep gray-scale power supply unchanged during the gray-scale
voltage output.
TEST = L: Normal operation mode
TEST = H: Test mode (OP AMP CUT-OFF, Rpd = 10kΩ)
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