K4S640832D Datasheet, PDF (7/10 Pages) Samsung semiconductor – 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL

K4S640832D
CMOS SDRAM
AC CHARACTERISTICS(AC operating conditions unless otherwise noted)
Parameter
CLK cycle time
CAS latency=3
CAS latency=2
CLK to valid
output delay
CAS latency=3
CAS latency=2
Output data
hold time
CAS latency=3
CAS latency=2
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
CAS latency=3
CAS latency=2
- 75
- 80
- 1H
- 1L
- 10
Symbol
Unit Note
Min Max Min Max Min Max Min Max Min Max
7.5
8
10
10
10
tCC
1000
1000
1000
1000
1000 ns 1
-
-
10
12
13
5.4
6
6
6
7
tSAC
ns 1,2
-
-
6
7
7
2.7
3
3
3
3
tOH
ns 2
-
-
3
3
3
tCH
2.5
3
3
3
3.5
ns 3
tCL
2.5
3
3
3
3.5
ns 3
tSS
1.5
2
2
2
2.5
ns 3
tSH
0.8
1
1
1
1.5
ns 3
tSLZ
1
1
1
1
1
ns 2
5.4
6
6
6
7
tSHZ
ns
-
-
6
7
7
Notes : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Output rise time
Symbol
Condition
Min
trh
Measure in linear
region : 1.2V ~1.8V
1.37
Typ
Max
4.37
Output fall time
tfh
Measure in linear
region : 1.2V ~1.8V
1.30
3.8
Output rise time
trh
Measure in linear
region : 1.2V ~1.8V
2.8
3.9
5.6
Output fall time
tfh
Measure in linear
region : 1.2V ~1.8V
2.0
2.9
5.0
Notes : _{1. Rise time specification based on 0pF + 50 Ohms to VSS, use these values to design to.}
2. Fall time specification based on 0pF + 50 Ohms to VDD, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to VSS.
Unit
Volts/ns
Volts/ns
Volts/ns
Volts/ns
Notes
3
3
1,2
1,2
Rev. 0.0 May 1999