K4S640832D Datasheet, PDF (2/10 Pages) Samsung semiconductor – 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL

K4S640832D
2M x 8Bit x 4 Banks Synchronous DRAM
CMOS SDRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K Cycle)
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The K4S640832D is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits,
fabricated with SAMSUNG′s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
ORDERING INFORMATION
Part No.
Max Freq. Interface Package
K4S640832D-TC/L75 133MHz(CL=3)
K4S640832D-TC/L80
K4S640832D-TC/L1H
K4S640832D-TC/L1L
125MHz(CL=3)
100MHz(CL=2)
100MHz(CL=3)
LVTTL
54
TSOP(II)
K4S640832D-TC/L10 66MHz(CL=2 &3)
Data Input Register
CLK
ADD
Bank Select
2M x 8
2M x 8
2M x 8
2M x 8
Column Decoder
LCKE
LRAS
LCBR
LWE
LCAS
Latency & Burst Length
Programming Register
LWCBR
Timing Register
LWE
LDQM
DQi
LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
* ^{Samsung Electronics reserves the right to change products or specification without notice.}
Rev. 0.0 May 1999