K4S281632D Datasheet, PDF (6/11 Pages) Samsung semiconductor – 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL

K4S281632D
CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Operating current
(One bank active)
Symbol
Test Condition
Burst length = 1
ICC1 tRC ≥ tRC(min)
IO = 0 mA
Version
Unit Note
-55 -60 -7C -75 -1H -1L
130 130 110 100 100 100 mA 1
Precharge standby cur-
rent in power-down mode
ICC2P CKE ≤ VIL(max), tCC = 10ns
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞
2
mA
2
Precharge standby cur-
ICC2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
20
rent in non power-down
mA
mode
ICC2NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
10
Active standby current in
power-down mode
ICC3P CKE ≤ VIL(max), tCC = 10ns
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞
5
mA
5
Active standby current in
ICC3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
30
mA
non power-down mode
(One bank active)
ICC3NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
25
mA
Operating current
(Burst mode)
IO = 0 mA
ICC4
Page burst
4Banks Activated
tCCD = 2CLKs
150 150 140 140 130 130 mA 1
Refresh current
ICC5 tRC ≥ tRC(min)
220 220 220 200 190 190 mA 2
Self refresh current
ICC6 CKE ≤ 0.2V
C
2
mA 3
L
800
uA 4
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S281632D-TC**
4. K4S281632D-TL**
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
Rev. 0.1 Sept. 2001