K4M563233D Datasheet, PDF (6/8 Pages) Samsung semiconductor – 8Mx32 Mobile SDRAM 90FBGA

K4M563233D-M(E)E/N/I/P
CMOS SDRAM
AC OPERATING TEST CONDITIONS (VDD = 2.7V ~ 3.6V, TA = -25°C to 85°C for Extended, -40°C to 85°C for Industrial)
Parameter
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
Unit
2.4/0.4
V
1.4
V
tr/tf = 1/1
ns
1.4
V
See Fig. 2
VDDQ
Vtt = 0.5 x VDDQ
Output
870 Ω
1200 Ω
30pF
VOH (DC) = 2.4V, I OH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Z0 = 50Ω
50 Ω
30pF
(Fig. 1) DC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
tR R D(min)
tR C D(min)
tR P(min)
t R A S( m i n )
tRAS(max)
tRC (min)
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tC C D(min)
CAS latency=3
CAS latency=2
CAS latency=1
(Fig. 2) AC output load circuit
Version
- 80
-1H
-1L
16
19
19
19
19
24
19
19
24
48
50
60
100
68
70
84
2
tRDL + tRP
1
1
1
2
1
-
0
Unit
ns
ns
ns
ns
us
ns
CLK
-
CLK
CLK
CLK
ea
Note
1
1
1
1
1
2,3
3
2
2
4
5
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. Minimum tRDL=2CLK and tDAL(=tRDL + tRP) is required to complete both of last data wite command(tRDL) and precharge
command(tRP). tRDL=1CLK can be supported only in the case under 100MHz with manual precharge mode.
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
Rev. 1.1 Dec. 2002