DS_K6F8016U6B Datasheet, PDF (6/9 Pages) Samsung semiconductor – 512K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM

K6F8016U6B Family
CMOS SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL)
Address
Data Out
tRC
tAA
tOH
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Address
CS1
tRC
tAA
tOH
tCO
CS2
UB, LB
OE
Data out
High-Z
tBA
tOE
tOLZ
tBLZ
tLZ
Data Valid
tHZ
tBHZ
tOHZ
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
Revision 1.0
September 2001