DS_K6X8016C3B Datasheet, PDF (5/9 Pages) Samsung semiconductor – 64Kx36 & 64Kx32-Bit Synchronous Pipelined Burst SRAM

K6X8016C3B Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level: 0.8 to 2.4V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): CL=100pF+1TTL
CL=50pF+1TTL
CL¹⁾
1.Including scope and jig capacitance
AC CHARACTERISTICS
(VCC=4.5~5.5V, Commercial product:TA=0 to 70°C, Industrial product:TA=-40 to 85°C, Automotive product:TA=-40 to 125°C)
Parameter List
Read
Write
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
LB, UB enable to low-Z output
Chip disable to high-Z output
Output Disable to High-Z Output
Output hold from address change
LB, UB valid to data output
UB, LB disable to high-Z output
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
LB, UB valid to end of write
Symbol
tRC
tAA
tCO
tOE
tLZ
tOLZ
tBLZ
tHZ
tOHZ
tOH
tBA
tBHZ
tWC
tCW
tAS
tAW
tWP
tWR
tWHZ
tDW
tDH
tOW
tBW
Speed Bins
55ns
70ns
Min
Max
Min
Max
55
-
70
-
-
55
-
70
-
55
-
70
-
25
-
35
10
-
10
-
5
-
5
-
5
-
5
-
0
20
0
25
0
20
0
25
10
-
10
-
-
25
-
35
0
20
0
25
55
-
70
-
45
-
60
-
0
-
0
-
45
-
60
-
40
-
55
-
0
-
0
-
0
20
0
25
20
-
30
-
0
-
0
-
5
-
5
-
45
-
60
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Vcc for data retention
VDR
CS≥Vcc-0.2V
Data retention current
K6X8016C3B-B
IDR
Vcc=3.0V, CS≥Vcc-0.2V
CS≥Vcc-0.2V
K6X8016C3B-F
K6X8016C3B-Q
Data retention set-up time
Recovery time
tSDR
tRDR
See data retention waveform
Min Typ Max Unit
2.0
-
5.5
V
-
-
15
-
-
15
µA
-
-
30
0
-
-
ms
5
-
-
5
Revision 1.0
September 2003