K8A56ETC Datasheet, PDF (44/64 Pages) Samsung semiconductor – 256Mb C-die NOR FLASH

K8A56(57)15ET(B)(Z)C
Rev. 1.0
datasheet ^{NOR FLASH MEMORY}
19.0 CROSSING OF FIRST WORD BOUNDARY IN BURST READ MODE
The additional clock insertion for word boundary is needed only at the first crossing of word boundary. This means that no additional clock cycle is needed
from 2nd word boundary crossing to the end of continuous burst read. Also, the number of additional clock cycle for the first word boundary can varies
from zero to thirteen cycles, and the exact number of additional clock cycle depends on the starting address of burst read and programmable wait state
settings.
For example, if the starting address is 16N+15 (the worst case) and programmable wait state setting(A<14:11>) is "0011" (which means data is valid on
the 7th active CLK edge after AVD transition to Vih), six additional clock cycle is needed.
Similarly, if the starting address is 16N+15 (the worst case) and programmable wait state setting(A<14:11>) is "0010" (which means data is valid on the
6th active CLK edge after AVD transition to Vih), five additional clock cycle is needed.
Below table shows the starting address vs. additional clock cycles for first word boundary.
Starting Address vs. Additional Clock Cycles for first word boundary
Srarting
Address Group
for
Burst Read
16N
The Residue of
(Address/16)
0
LSB Bits
of
Address
Additional Clock Cycles for First Word Boundary (note1)
A<14:11> "0000" A<14:11> "0001" A<14:11> "0010"
Valid data : 4th CLK Valid data : 5th CLK Valid data : 6th CLK
...
A<14:11> "1010"
Valid data : 14th CLK
0000
0 cycle
0 cycle
0 cycle
...
0 cycle
16N+1
1
0001
0 cycle
0 cycle
0 cycle
...
0 cycle
16N+2
2
0010
0 cycle
0 cycle
0 cycle
...
0 cycle
16N+3
3
0011
0 cycle
0 cycle
0 cycle
...
1 cycle
16N+4
4
0100
0 cycle
0 cycle
0 cycle
...
2 cycle
16N+5
5
0101
0 cycle
0 cycle
0 cycle
...
3 cycle
16N+6
6
0110
0 cycle
0 cycle
0 cycle
...
4 cycle
16N+7
7
0111
0 cycle
0 cycle
0 cycle
...
5 cycle
16N+8
8
1000
0 cycle
0 cycle
0 cycle
...
6 cycle
16N+9
9
1001
0 cycle
0 cycle
0 cycle
...
7 cycle
16N+10
10
1010
0 cycle
0 cycle
0 cycle
...
8 cycle
16N+11
11
1011
0 cycle
0 cycle
1 cycle
...
9 cycle
16N+12
12
1100
0 cycle
1 cycle
2 cycle
...
10 cycle
16N+13
13
1101
1 cycle
2 cycle
3 cycle
...
11 cycle
16N+14
14
1110
2 cycle
3 cycle
4 cycle
...
12 cycle
16N+15
15
1111
3 cycle
4 cycle
5 cycle
...
13 cycle
NOTE :
Address bit A<14:11> means the programmable wait state on burst mode configuration register. Refer to Table 10.
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