K8A56ETC Datasheet, PDF (17/64 Pages) Samsung semiconductor – 256Mb C-die NOR FLASH

K8A56(57)15ET(B)(Z)C
Rev. 1.0
datasheet ^{NOR FLASH MEMORY}
9.5 Autoselect Mode
By writing the autoselect command sequences to the system, the device enters the autoselect mode. This mode can be read only by asynchronous read
mode. The system can then read autoselect codes from the internal register(which is separate from the memory array). Standard asynchronous read
cycle timings apply in this mode. The device offers the Autoselect mode to identify manufacturer and device type by reading a binary code. In addition,
this mode allows the host system to verify the block protection or unprotection. Table 13 shows the address and data requirements. The autoselect com-
mand sequence may be written to an address within a bank that is in the read mode, erase-suspend-read mode or program-suspend-read mode. The
autoselect command may not be written while the device is actively programming or erasing in the device. The autoselect command sequence is initiated
by first writing two unlock cycles. This is followed by a third write cycle that contains the address and the autoselect command. Note that the block
address is needed for the verification of block protection. The system may read at any address within the same bank any number of times without initiat-
ing another autoselect command sequence. And the burst read should be prohibited during Autoselect Mode. To terminate the autoselect operation, write
Reset command(F0H) into the command register.
[Table 13] Autoselect Mode Description
Description
Address
Manufacturer ID
(DA) + 00H
Device ID
(DA) + 01H
Block Protection/Unprotection (BA) + 02H
Handshaking
(DA) + 03H
Read Data
ECH
2206H (Top Boot Block), 2207H (Bottom Boot Block), 301BH (Uniform Block)
01H (protected), 00H (unprotected)
0H : handshaking, 1H : non-handshaking
9.6 Standby Mode
When the CE inputs is held at VCC ± 0.2V, and the system is not reading or writing, the device enters Stand-by mode to minimize the power consumption.
In this mode, the device outputs are placed in the high impedence state, independent of the OE input. When the device is in either of these standby
modes, the device requires standard access time (tCE) for read access before it is ready to read data. If the device is deselected during erasure or pro-
gramming, the device draws active current until the operation is completed. ICC5 in the DC Characteristics table represents the standby current specifica-
tion.
9.7 Automatic Sleep Mode
The device features Automatic Sleep Mode to minimize the device power consumption during both asynchronous and burst mode. When addresses
remain stable for tAA+60ns, the device automatically enables this mode. The Automatic sleep mode is depends on the CE, WE and OE signal, so CE,
WE and OE signals are held at any state. In a sleep mode, output data is latched and always available to the system. When OE is active, the device pro-
vides new data without wait time. Automatic sleep mode current is equal to standby mode current.
9.8 Output Disable Mode
When the OE input is at VIH , output from the device is disabled. The outputs are placed in the high impedance state.
9.9 Block Protection & Unprotection
To protect the block from accidental writes, the block protection/unprotection command sequence is used. On power up, all blocks in the device are pro-
tected. To unprotect a block, the system must write the block protection/unprotection command sequence. The first two cycles are written: addresses are
don’t care and data is 60h. Using the third cycle, the block address (ABP) and command (60h) is written, while specifying with addresses A6, A1 and A0
whether that block should be protected (A6 = VIL, A1 = VIH, A0 = VIL) or unprotected (A6 = VIH, A1 = VIH, A0 = VIL). After the third cycle, the system can
continue to protect or unprotect additional cycles, or exit the sequence by writing F0h (reset command).
The device offers three types of data protection at the block level:
• The block protection/unprotection command sequence disables or re-enables both program and erase operations in any block.
• When WP is at VIL, the two outermost blocks are protected.(Boot block part : K8A(54/55/56/57)15ET(B)C)
• When WP is at VIL, the last one block (BA255) is protected.(Uniform block part :K8A(54/55/56/57)15EZC)
• When VPP is at VIL, all blocks are protected.
Note that user never float the Vpp and WP, that is, Vpp is always connected with VIH, VIL or VID and WP is VIH or VIL.
9.10 Hardware Reset
The device features a hardware method of resetting the device by the RESET input. When the RESET pin is held low(VIL) for at least a period of tRP, the
device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write commands for the duration of the RESET pulse.
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