DS_M390S2858CT1 Datasheet, PDF (4/12 Pages) Samsung semiconductor – SDRAM DIMM

M390S2858CT1
PC133 Registered DIMM
STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)
*1. Register Input
01
CLK
23
*2
*1
REG
Control Signal(RAS,CAS,WE)
*3 DOUT
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
RAS
CAS
WE
*2. Register Output
RAS
td
CAS
WE
*3. SDRAM
DQ
tr
tRAC(refer to *1)
tRAC(refer to *2)
CAS latency(refer to *1)
=2CLK+1CLK
tSAC
Qa0 Qa1 Qa2 Qa3
CAS latency(refer to *2)
=2CLK
Row Active Read
Command
Precharge
Command
td
tr
1CLK
Db0 Db1 Db2 Db3
tRDL
Row Active Write
Command
Precharge
Command
td, tr = Delay of register (74ALVCF162835)
Notes : 1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal
because of the buffering in register (74ALVCF162835). Therefore, Input/Output signals of read/write function should be
issued 1CLK earlier as compared to Unbuffered DIMMs.
2. DIN is to be issued 1clock after write command in external timing because DIN is issued directly to module.
: Don′t care
REV. 0.1 Sept. 2001