DS_M390S2858CT1 Datasheet, PDF (11/12 Pages) Samsung semiconductor – SDRAM DIMM

M390S2858CT1
M390S2858CT1-C7A/C7C
•Organization : 128MX72
•Composition : 128MX4 * 18ea
•Used component part # : K4S510632C-TC75/C7C
•# of banks in module : 2 Rows
•# of banks in component : 4 banks
•Feature : 1,700 mil height & double sided
•Refresh : 8K/64ms
•Contents :
Byte #
Function described
0 # of bytes written into serial memory at module manufacturer
1 Total # of bytes of SPD memory device
2 Fundamental memory type
3 # of row address on this assembly
4 # of column address on this assembly
5 # of module Rows on this assembly
6 Data width of this assembly
7 ...... Data width of this assembly
8 Voltage interface standard of this assembly
9 SDRAM cycle time from clock @CAS latency of 3
10 SDRAM access time from clock @CAS latency of 3
11 DIMM configuration type
12 Refresh rate & type
13 Primary SDRAM width
14 Error checking SDRAM width
15 Minimum clock delay for back-to-back random column address
16 SDRAM device attributes : Burst lengths supported
17 SDRAM device attributes : # of banks on SDRAM device
18 SDRAM device attributes : CAS latency
19 SDRAM device attributes : CS latency
20 SDRAM device attributes : Write latency
21 SDRAM module attributes
22 SDRAM device attributes : General
23 SDRAM cycle time @CAS latency of 2
24 SDRAM access time @CAS latency of 2
25 SDRAM cycle time @CAS latency of 1
26 SDRAM access time @CAS latency of 1
27 Minimum row precharge time (=tRP)
28 Minimum row active to row active delay (tRRD)
29 Minimum RAS to CAS delay (=tRCD)
30 Minimum activate precharge time (=tRAS)
31 Module Row density
32 Command and Address signal input setup time
33 Command and Address signal input hold time
34 Data signal input setup time
PC133 Registered DIMM
Function Supported
-7C
-7A
128bytes
256bytes (2K-bit)
SDRAM
13
11
2 Rows
72 bits
-
LVTTL
7.5ns
5.4ns
ECC
7.8us, support self refresh
x4
x4
tCCD = 1CLK
1, 2, 4, 8 & full page
4 banks
2&3
0 CLK
0 CLK
Registered/Buffered DQM,
address & control inputs and
On-card PLL
+/- 10% voltage tolerance,
Burst Read Single bit Write
precharge all, auto precharge
7.5ns
10ns
5.4ns
6ns
-
-
-
-
15ns
20ns
15ns
15ns
15ns
20ns
45ns
45ns
2 Rows of 512MB
1.5ns
0.8ns
1.5ns
Hex value
-7C
-7A
80h
08h
04h
0Dh
0Bh
02h
48h
00h
01h
75h
54h
02h
82h
04h
04h
01h
8Fh
04h
06h
01h
01h
1Fh
Note
1
1
2
2
0Eh
75h
A0h
2
54h
60h
2
00h
00h
2
00h
00h
2
0Fh
14h
0Fh
0Fh
0Fh
14h
2Dh
2Dh
80h
15h
08h
15h
REV. 0.1 Sept. 2001