K4S560432E-UC Datasheet, PDF (3/14 Pages) Samsung semiconductor – 256Mb E-die SDRAM Specification 54 TSOP-II with Pb-Free (RoHS compliant)

SDRAM 256Mb E-die (x4, x8, x16)
CMOS SDRAM
16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks / 4M x 16Bit x 4 Banks SDRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (8K Cycle)
• 54 TSOP(II) Pb-free Package
• RoHS compliant
GENERAL DESCRIPTION
The K4S560432E / K4S560832E / K4S561632E is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x
16,785,216 / 4 x 8,392,608 / 4 x 4,196,304 words by 4bits, fabricated with SAMSUNG's high performance CMOS technology. Synchro-
nous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of oper-
ating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high
bandwidth, high performance memory system applications.
Ordering Information
Part No.
K4S560432E-UC(L)75
K4S560832E-UC(L)75
K4S561632E-UC(L)60/75
Orgainization
64M x 4
32M x 8
16M x 16
Max Freq.
133MHz
133MHz
133MHz
Interface
LVTTL
LVTTL
LVTTL
Package
54pin TSOP(II)
54pin TSOP(II)
54pin TSOP(II)
Organization
64Mx4
32Mx8
16Mx16
Row Address
A0~A12
A0~A12
A0~A12
Column Address
A0-A9, A11
A0-A9
A0-A8
Row & Column address configuration
Rev. 1.3 August 2004