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K4H560438E-ZC Datasheet, PDF (3/23 Pages) Samsung semiconductor – 256Mb E-die DDR SDRAM Specification 60 FBGA with Pb-Free (RoHS compliant) | |||
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DDR SDRAM 256Mb E-die (x4, x8) Pb-Free
DDR SDRAM
Key Features
⢠Double-data-rate architecture; two data transfers per clock cycle
⢠Bidirectional data strobe [DQ] (x4,x8) Four banks operation
⢠Differential clock inputs(CK and CK)
⢠DLL aligns DQ and DQS transition with CK transition
⢠MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
⢠All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
⢠Data I/O transactions on both edges of data strobe
⢠Edge aligned data output, center aligned data input
⢠DM for write masking only (x4, x8)
⢠Auto & Self refresh
⢠7.8us refresh interval(8K/64ms refresh)
⢠Maximum burst refresh cycle : 8
⢠60Ball FBGA Pb-Free package
⢠RoHS compliant
Ordering Information
Part No.
K4H560438E-ZC/LB3
K4H560438E-ZC/LA2
K4H560438E-ZC/LB0
K4H560838E-ZC/LB3
K4H560838E-ZC/LA2
K4H560838E-ZC/LB0
Org.
64M x 4
32M x 8
Max Freq.
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
Interface
SSTL2
SSTL2
Package
60 FBGA
60 FBGA
Operating Frequencies
CL-tRCD-tRP
Speed @CL2
Speed @CL2.5
B3(DDR333@CL=2.5)
2.5-3-3
133MHz
166MHz
*CL : CAS Latency
A2(DDR266@CL=2)
2-3-3
133MHz
133MHz
B0(DDR266@CL=2.5)
2.5-3-3
100MHz
133MHz
Rev. 1.1 October, 2004
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