K4H1G0438M Datasheet, PDF (3/23 Pages) Samsung semiconductor – 1Gb M-die DDR SDRAM Specification

DDR SDRAM 1Gb M-die (x4, x8)
DDR SDRAM
Key Features
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• tRFC(Refresh row cycle time) = 120ns
• Maximum burst refresh cycle : 8
• 66pin TSOP II package
Ordering Information
Part No.
K4H1G0438M-TC/LB3
K4H1G0438M-TC/LA2
K4H1G0438M-TC/LB0
K4H1G0838M-TC/LB3
K4H1G0838M-TC/LA2
K4H1G0838M-TC/LB0
Org.
256M x 4
128M x 8
Max Freq.
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
Interface
Package
SSTL2
66pin TSOP II
Operating Frequencies
Speed @CL2
Speed @CL2.5
*CL : CAS Latency
B3(DDR333@CL=2.5)
133MHz
166MHz
A2(DDR266@CL=2.0)
133MHz
133MHz
B0(DDR266@CL=2.5)
100MHz
133MHz
Revision 1.0 October, 2004