S3C3410X Datasheet, PDF (259/314 Pages) Samsung semiconductor – 16-Bit CMOS Microcontrollers

S3C3410X RISC MICROPROCESSOR
INTERRUPT CONTROLLER
INTERRUPT VECTOR BASE ADDRESS
To reduce the interrupt latency, the S3C3410X can support the concept of interrupt vector base address. The
interrupt vector base address means the start address of corresponding service routine. In other word, as soon as
CPU recognize the interrupt request, there will be Branch to fixed hardwired vector. But, because the CPU can
support just two interrupt mode of FIQ and IRQ, we need special technique to assign the specific base vector
address for all interrupt source. To do this, the interrupt controller should give the Branch Instruction (Branch to
the fixed hardware vector address) to CPU as soon as the CPU recognize the interrupt request. Because the
interrupt controller can know the interrupt mode as well as source, the interrupt controller can give the specific
vector address to CPU by H/W. Following table shows the interrupt base vector address for each interrupt source.
Sources
EINT0
EINT1
INT_URX
INT_UTX
INT_UERR
INT_DMA0
INT_DMA1
INT_TOF0
INT_TMC0
INT_TOF1
INT_TMC1
INT_TOF2
INT_TMC2
INT_TOF3
INT_TMC3
INT_TOF4
Address
0x80
0x84
0x88
0x8c
0x90
0x94
0x98
0x9c
0xa0
0xa4
0xa8
0xac
0xb0
0xb4
0xb8
0xbc
Sources
INT_TMC4
INT_BT
INT_SIO0
INT_SIO1
INT_IIC
INT_RTCA
INT_RTCT
INT_TF
EINT2
EINT3
EINT4/5/6/7
INT_ADC
EINT8
EINT9
EINT10
EINT11
Address
0xc0
0xc4
0xc8
0xcc
0xd0
0xd4
0xd8
0xdc
0xe0
0xe4
0xe8
0xec
0xf0
0xf4
0xf8
0xfc
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