S3C3410X Datasheet, PDF (146/314 Pages) Samsung semiconductor – 16-Bit CMOS Microcontrollers

SYSTEM MANAGER
S3C3410X RISC MICROPROCESSOR
BANK TIMING CONTROL REGISTER (BANKCONx: nRAS0 – nRAS1)
Register
BANKCON6
BANKCON7
Offset
Address
0x2018
0x201c
R/W
Description
R/W Bank 6 control register (for FP/EDO/SDRAM/ROM/Flash/SRAM)
R/W Bank 7 control register (for FP/EDO/SDRAM/ROM/Flash/SRAM)
Reset
Value
0x0
0x0
NOTE: BANKCON6 and 7 register can have dual configuration, depending on the MT field in SYSCFG register. In other
word, BANKCON6 and 7 have the same configuration with BANKCON1,2,3,4 and 5 when MT=00, or BANKCON6
and 7 have the configuration on DRAM(FP, EDO)/SDRAM when MT=01, 10, and 11.
BANKCONx
Bit
Description
Memory Type = ROM or SRAM [MT=00 in SYSCFG]
DBW
[0] Data Bus Width: This bit determines the physical data bus width
for bankx (bank6 and 7)
0 = 8-bit
1 = 16-bit
PMC
[2:1] These bits determines the page mode configuration for ROM
access (Single mode, 4 data page mode, 8 data page mode, and
16 data page mode).
00 = 1 Data 01 = 4 Data 10 = 8 Data 11 = 16 Data
SM
[3] In certain x16 SRAM, there are byte selection signals such as LB
(Lowe Byte) and UB (Upper Byte). In this case, nWE from
S3C3410X should be connected to WE of SRAM and nWBE[1:0]
from S3C3410X should be connected to UB/LB of SRAM.
0 = Ordinary
1 = x16 type SRAM
Tacc
[6:4] Determine the number of Access Cycle (Tacc). Please refer the
timing diagram.
000 = Disable 001 = 2 Clock 010 = 3 Clock 011 = 4 Clock
100 = 5 Clock 101 = 6 Clock 110 = 7 Clock 111 = 10 Clock
Tacp
[8:7] Determine the number of Page mode access cycle @ page mode
(Tacp). Please refer the timing diagram.
00 = 5 Clock 01 = 2 Clock 10 = 3 Clock 11 = 4 Clock
Reserved
[9] Reserved
Initial State
0
00
0
000
00
0
4-10