S6A0074 Datasheet, PDF (24/68 Pages) Samsung semiconductor – 34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0074
34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Instruction RE
Table 6. Instruction Set 1 (Continued)
Instruction Code
Description
Executi
on Time
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(fosc =
270kHz)
Function
set
0 0 0 0 0 1 DL N RE DH REV Set interface data length
(0)
(DL = "1": 8-bit, DL = "0": 4-bit),
numbers of display line when
NW = "0",
(N = "1": 2-line, N = "0" : 1-line),
extension register, RE("0"),
shift/scroll enable
DH = "1": display shift enable
DH = "0": dot scroll enable.
39µs
reverse bit
REV = "1": reverse display,
REV = "0": normal display.
1 0 00 ⁰
1 DL N RE BE 0 Set DL, N, RE("1") and
(1)
CGRAM/SEGRAM blink enable
(BE)
BE = "1/0": CGRAM/SEGRAM
blink enable/disable
39µs
Set
CGRAM
address
0 0 0 0 1 ^{AC5 AC4 AC3 AC2 AC1 AC0} Set CGRAM address in address ^39µs
counter.
Set
1 0 0 0 1 X X AC3 AC2 AC1 AC0 Set SEGRAM address in address ^39µs
SEGRAM
counter.
address
Set
DDRAM
address
0 0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address
counter.
39µs
Set scroll 1 0 0 1 X QC5 QC4 QC3 QC2 QC1 QC0 Set the quantity of horizontal dot
quantity
scroll.
39µs
Read busy X 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 Can be known whether during
0µs
flag and
internal operation or not by
address
reading BF. The contents of
address counter can also be read.
BF = "1": busy state,
BF = "0": ready state.
Write data X 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Write data into internal RAM
(DDRAM / CGRAM / SEGRAM).
43µs
Read data X 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Read data from internal RAM
(DDRAM / CGRAM / SEGRAM).
43µs
"X": Don’t care
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