K8P5616UZB Datasheet, PDF (22/60 Pages) Samsung semiconductor – 256Mb B-die Page NOR FLASH

K8P5616UZB
Rev. 1.0
datasheet NOR FLASH MEMORY
10.13 Power-up Protection
To avoid initiation of a write cycle during Vcc Power-up, RESET low must be asserted during power-up. After RESET goes high, the device is reset to the
read mode.
10.14 Low Vcc Write Inhibit
To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for Vcc less than 2.3V. If Vcc < VLKO (Lock-Out Volt-
age), the command register and all internal program/erase circuits are disabled. Under this condition the device will reset itself to the read mode. Subse-
quent writes will be ignored until the Vcc level is greater than VLKO. It is the user′s responsibility to ensure that the control pins are logically correct to
prevent unintentional writes when Vcc is above 2.3V.
10.15 Write Pulse Glitch Protection
Noise pulses of less than 5ns(typical) on CE, OE, or WE will not initiate a write cycle.
10.16 Logical Inhibit
Writing is inhibited under any one of the following conditions : OE = VIL, CE = VIH or WE = VIH. To initiate a write, CE and WE must be "0", while OE is
"1".
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