K4H560438D-TC Datasheet, PDF (17/25 Pages) Samsung semiconductor – 256Mb

K4H560838D
DDR SDRAM
Parameter
Symbol
-TC/LB3
(DDR333)
Min Max
-TC/LA2
(DDR266A)
Min Max
-TC/LB0
(DDR266B)
Min Max
-TC/LA0
(DDR200)
Min Max
Unit Note
Mode register set cycle time
tMRD
12
15
15
16
ns
DQ & DM setup time to DQS
tDS
0.45
0.5
0.5
0.6
ns 7,8,9
DQ & DM hold time to DQS
tDH
0.45
0.5
0.5
0.6
ns _7,8,9
Control & Address input pulse width
tIPW
2.2
2.2
2.2
2.5
ns
DQ & DM input pulse width
tDIPW 1.75
1.75
1.75
2
ns
Power down exit time
tPDEX
6
7.5
7.5
10
ns
Exit self refresh to non-Read command tXSNR
75
75
75
80
ns
4
Exit self refresh to read command
tXSRD
200
200
200
200
tCK
Refresh interval time
tREFI
7.8
7.8
7.8
7.8
us
1
Output DQS valid window
tQH
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
ns
5
Clock half period
tHP
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
ns
Data hold skew factor
tQHS
0.55
0.75
0.75
0.8
ns
DQS write postamble time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6 tCK 3
Active to Read with Auto precharge
command
tRAP
18
20
20
20
Autoprecharge write recovery +
Precharge time
tDAL
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
tCK 11
1. Maximum burst refresh cycle : 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
4. A write command can be applied with tRCD satisfied after this command.
5. For registered DIMMs, tCL and tCH are ≥ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period
jitter due to crosstalk (tJIT(crosstalk)) on the DIMM.
6. Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
∆tIS
∆tIH
(V/ns)
(ps)
(ps)
0.5
0
0
0.4
+50
+50
0.3
+100
+100
This derating table is used to increase t_IS/t_IH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate
based on the lesser of AC-AC slew rate and DC-DC slew rate.
7. I/O Setup/Hold Slew Rate Derating
I/O Setup/Hold Slew Rate
∆tDS
∆tDH
(V/ns)
(ps)
(ps)
0.5
0
0
0.4
+75
+75
0.3
+150
+150
This derating table is used to increase t_DS/t_DH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate
based on the lesser of AC-AC slew rate and DC-DC slew rate.
Rev. 0.4 May. 2002
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