K4H560438D-TC Datasheet, PDF (15/25 Pages) Samsung semiconductor – 256Mb

K4H560838D
DDR SDRAM
Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on
VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise
coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH.
2. V_TT is not applied directly to the device. V_TT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
DDR SDRAM IDD spec table
(VDD=2.7V, T = 10°C)
Symbol
K4H560838D-TC/LB3
(DDR333)
IDD0
90
IDD1
120
IDD2P
3
IDD2F
25
IDD2Q
20
IDD3P
35
IDD3N
55
IDD4R
170
IDD4W
170
IDD5
180
IDD6
Normal
3
Low power
1.5
IDD7A
325
AC Operating Conditions
32Mx8
K4H560838D-TC/LA2, CB0
(DDR266A/B)
80
110
3
20
18
30
45
140
140
165
3
1.5
280
K4H560838D-TC/LA0
(DDR200)
75
100
3
18
16
25
40
120
115
150
3
1.5
235
Unit Notes
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA Optional
mA
Parameter/Condition
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
Symbol
Min
Max
Unit
VIH(AC) VREF + 0.31
V
VIL(AC)
VREF - 0.31
V
VID(AC)
0.7
VDDQ+0.6
V
VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2
V
Note
3
3
1
2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V_IX is expected to equal 0.5*V_DDQ of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simu
lation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Overshoot/Undershoot specification
Parameter
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
The area between the overshoot signal and VDD must be less than or equal to
The area between the undershoot signal and GND must be less than or equal to
- 15 -
Specification
Address &
Control pins
Data pins
1.6 V
1.2V
1.6 V
1.2V
4.5 V-ns
2.5 V-ns
4.5 V-ns
2.5 V-ns
Rev. 0.4 May. 2002