M470L3324BT Datasheet, PDF (12/20 Pages) Samsung semiconductor – DDR SDRAM Unbuffered Module 18 4 pin Unbuffered Module based on 512Mb B-die

256MB, 512MB, 1GB Unbuffered SODIMM
DDR SDRAM
10.0 AC Operating Conditions
Parameter/Condition
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
Symbol
Min
Max
Unit
VIH(AC) VREF + 0.31
V
VIL(AC)
VREF - 0.31
V
VID(AC)
0.7
VDDQ+0.6
V
VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2
V
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V_IX is expected to equal 0.5*V_DDQ of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in
simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Note
3
3
1
2
Vtt=0.5*VDDQ
Output
RT=50Ω
Z0=50Ω
CLOAD=30pF
VREF
=0.5*VDDQ
Output Load Circuit (SSTL_2)
11.0 Input/Output Capacitance
( TA= 25°C, f=100MHz)
Parameter
M470L3324BT(U) M470L6524BT(U) M470L2923BN(V)
Symbol
Unit
Min
Max
Min
Max
Min
Max
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) CIN1
41
45
49
57
65
81
pF
Input capacitance(CKE0,CKE1)
CIN2
34
38
42
50
42
50
pF
Input capacitance( CS0, CS1)
CIN3
34
38
42
50
42
50
pF
Input capacitance( CLK0, CLK1,CLK2)
CIN4
25
30
25
30
28
34
pF
Input capacitance(DM0~DM7)
CIN5
6
7
6
7
10
12
pF
Data & DQS input/output capacitance(DQ0~DQ63)
Cout1
6
7
6
7
10
12
pF
Rev. 1.5 June 2005