SA3488 Datasheet, PDF (13/20 Pages) Sames – CMOS 256 X 256 DIGITAL SWITCHING MATRIX

SA3488
During a very long internal operation (device initialization after RESET going high or
execution of instruction 6) a new set of data bytes with a valid opcode is accepted while
a wrong code is rejected. At the end of the current routine execution takes place in the
same way as described before.
At the end of an instruction it is normally recommended to read one or both registers. To
enable instruction 6, however, it is necessary to read register OR2. This is because
instruction 6, used between other short instructions of type 1 to 5, must have a lower
priority and can be enabled only after the short instructions have been completed.
Instruction 6 normally has a long process and a special flow which is described below.
First a not-all-zero mask is stored in the “expected messages” register and in another
“background” register. This operation starts the second phase of instruction 6 which is
called “channel 0 extraction” and is repeated at the beginning of any new time frame. At
the beginning of the time frame a new copy of activated channels to be extracted is made
from the “background register” and put in the “expected messages” register. In addition
the latter register is modified to indicate the exact number of messages that have arrived.
The term messages covers any input 0 channel data with starting sequence different
from the label 01. So using this label the number of expected messages can be reduced
to correspond to the number of effective messages. If and only if the residual number
is different from zero will the device start the extraction protocol at the end of the current
routine.
The procedure is as follows: the DR output is pulsed low as a two cycle interrupt request
and OR2 is loaded with the total number of active channels to be extracted.
The transfer of OR2 contents to the microprocessor continues the extraction which
consists of repeated steps of OR1 and OR2 loading, indicating respectively the message
and the incoming bus number. Reading the registers in the order OR1, OR2 must be
continued until completion or until the time frame runs out.
With a new time frame a new extraction process begins, resuming the copy operation
from the background register.
During extraction the active channels are scanned from the highest to the lowest number
(from 7 to 0). While extraction is being carried out the time interval requirements between
active rising edges of RD are a minimum of 5 to 13 t_CK for sequence OR2 - OR1 and a
minimum of 3 times t for sequence OR1 - OR2. More details are given in the following
CK
tables.
sames
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