SA3488 Datasheet, PDF (11/20 Pages) Sames – CMOS 256 X 256 DIGITAL SWITCHING MATRIX

SA3488
FUNCTIONAL OVERVIEW
The SA3488 is intended for large telephone switching systems, mainly central exchanges,
digital line concentrators and private branch exchanges where a distributed microcomputer
control approach is extensively used. It consists of a speech memory (SM), a control
memory (CM), a serial/parallel and a parallel/serial converter, an internal parallel bus,
an interface (8 data lines, 11 control signals) and dedicated logic. By means of repeated
clock division two time bases are generated. These are preset from an external
synchronization signal to two specific count numbers so that sequential scanning of the
bases give synchronous addresses to the memories and I/O channel controls. Different
preset count numbers are needed because of processing delays and data path direction.
The time-base for output channels is advanced with respect to the actual time. Each
serial PCM input channel is converted to parallel data and stored in the speech memory
at the beginning of any new time slot (according to first timebase) in the location
determined by input pin number and time slot number. The control memory CM
maintains the correspondences between input and output channels. More exactly, for
any output pin/output channel combination the control memory gives either the full
address of the speech memory location involved in the PCM transfer or an 8-bit word to
be supplied to the parallel/serial output converter. A 9^th bit at each CM location defines
the data source for output links; low for SM, high for CM.
The late timebase is used to scan the output channels and to determine the pins to be
serviced within each channel. Enough idle cycles are left to the microprocessor for
synchronous instruction processing. Two 8-bit registers OR1 and OR2 supply feedback
data for control or diagnostic purposes; OR1 comes from the internal bus i.e. from
memories, while OR2 gives an opcode copy and additional data to the microcomputer.
A four byte, 5-bit stack register and an instruction register, under microcomputer control,
store input data available at the interface.
Dedicated logic, under control of the microprocessor interface, extracts the 0 channel
content of any selected PCM input bus, using spare cycles of SM.
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