SA3488 Datasheet, PDF (12/20 Pages) Sames – CMOS 256 X 256 DIGITAL SWITCHING MATRIX

SA3488
FUNCTIONAL DESCRIPTION OF SPECIFIC MICROPROCESSOR OPERATIONS
The device, under microprocessor control, performs the following instructions:
1 CHANNEL CONNECTION/DISCONNECTION
2 CHANNEL DISCONNECTION
3 INSERTION OF A BYTE ON A PCM OUTPUT CHANNEL/CHANNEL
DISCONNECTION)
4 TRANSFER OF A SINGLE OUTPUT CHANNEL SAMPLE
5 TRANSFER OF A SINGLE OUTPUT CHANNEL CONTROL WORD
6 TRANSFER OF SELECTED 0 CHANNEL PCM INPUT DATA ACCORDING TO AN
8-BIT MASK PREVIOUSLY STORED IN THE “EXPECTED MESSAGES”
REGISTER.
The instruction flow is as follows:
Any input protocol is started by the microprocessor interface loading the internal stack
register with 2 bytes (4 bytes for instructions 1 and 3) qualified as data bytes by C/D =
0 and a specific opcode qualified by C/D = 1 (match condition is normally needed).
After the code is loaded, the instruction register is immediately checked to see whether
it is acceptable; if not, it is rejected. If accepted the instruction is also processed as
regards match condition and is appended for execution during the memories’ space
cycles.
Four cases are possible:
a) the code is not valid; execution cannot take place, the DR output pin is reset to
indicate the error and all registers are saved;
b) the code is valid for types 2, 4 and 6 but it is unmatched; execution cannot take place,
and DR is not affected.
c) the code is valid for types 1 and 3 and it is unmatched; the instruction is interpreted
as a channel disconnection.
d) the code is valid and it either matches or is of type 5; the instruction is processed as
received.
Validation control takes only two cycles out of a total execution time of 5 to 13 cycles;
the last operation is the updating of the contents of registers OR1 and OR2.
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