BU7858KN_07 Datasheet, PDF (9/25 Pages) Rohm – Mixer & Selector With 16bit D/A Converters

●DIGITAL INTERFACE OF 16BIT AUDIO D/A CONVERTER
16bit audio D/A converter equipped with this series can be used with the following audio format.
【BU7858KN】
1) MSB first 16bit data (Right justified)
LRCLK(fs)
Lch
Rch
BCLK(64fs）
SDTI
21 0
Don’t Care
15 14 _{13 12 11 4 3 2 1 0}
Don’t Care
15 14 13 12 11 ₄ 3 2 1 0
15:MSB, 0:LSB
2) MSB first 18bit data (Right justified)
LRCLK(fs)
Lch
Rch
BCLK(64fs）
SDTI
21 0
Don’t Care
17 16 _{15 14 11 4 3 2 1 0}
Don’t Care
17 16 15 14 11 ₄ 3 2 1 0
17:MSB, 0:LSB
3) IIS mode 18bit data (Left justified)
LRCK(fs)
Lch
Rch
BCLK(64fs)
SDTI
Don’t
17 16
4 3210
Don’t Care
4) IIS mode 16bit data (BCLK=32fs)
LRCLK(fs)
Lch
17:MSB, 0:LSB
17 16
43 2 10
Don’t Care
17 16
Rch
BCLK(32fs)
SDTI
2 1 0 15 14 13 12 11 10 9 8 7 6
3 2 1 0 15 14 13 12 11 10 9 8 7 6
3 2 1 0 15 14 13
15:MSB, 0:LSB
Fig.28 AUDIO I/F FORMAT (BU7858KN)
BU7858KN is provided with a mode that generates MCLK (Master Clock) by using the built-in PLL, so it is possible to
make a D/A converter operate even if the clocks are only BCLK (64fs/32fs), LRCLK (fs).
The PLL generates MCLK (Master Clock), which is necessary for driving of D/A converter, from BCLK (Bit Clock).
Please connect a capacitor (PLLC) for the filter with DVSS. Moreover, please place the capacitor nearest DVSS of IC in
order to reduce the noise interference.
Then it is possible to monitor the master clock that is generated internally from MCLKO, which is after all the monitor
terminal, and hence does not guarantee drivability and phase-margin.
Please tie the MCLKI terminal to DVSS when PLL is used. And please tie the PLLC terminal to DVSS when PLL is not
used. Moreover, it is not necessary to set the ”PLLPDN” and “SMPR” when PLL is not used.
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