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BU7858KN_07 Datasheet, PDF (17/25 Pages) Rohm – Mixer & Selector With 16bit D/A Converters | |||
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Matrix
No.
Pin Name I/O
No.
Pin Function
Terminal
Conditions
at Reset
Power
Equivalent
Circuit
Diagram
1 E3
AVDD
- Analog Power Supply
ï¼
AVDD
ï¼
2 C6
AVSS
- Analog Ground
ï¼
AVDD
ï¼
3 E6
ANAINL
I DAC L-ch Input
ï¼
AVDD
G
4 D6
ANAINR
I DAC R-ch Input
ï¼
AVDD
G
5 A3
HPOL
O Headphone Amplifier Output L-ch
Pull-down
AVDD
H
6 A2
HPOR
O Headphone Amplifier Output R-ch
Pull-down
AVDD
H
Low-band Correction Capacitor for Headphone
7 B4
CCL
I
Pull-down
AVDD
I
Amplifier L-ch
Low-band Correction Capacitor for Headphone
8 B1
CCR
I
Pull-down
AVDD
I
Amplifier R-ch
9 A5
SPOL
O L-ch Line Output for Speaker
Pull-down
AVDD
H
10 B5
SPOR
O R-ch Line Output for Speaker
Pull-down
AVDD
H
11 D5
COMOUT O Analog Reference Voltage Output
Hi-Z
AVDD
J
12 B6
COMIN
I Analog Reference Voltage Input
Hi-Z
AVDD
K
Capacitor Connection Terminal for Pop Noise
13 A4
CPOP
I/O
Hi-Z
AVDD
L
Reduction
Capacitor Connection Terminal for Noise
14 C5
CSTEP I/O
Hi-Z
AVDD
L
Reduction during Volume Change
15 E2
PLLC
I/O Capacitor Connection Terminal for PLL Loop Filter
ï¼
AVDD
L
16 E4 DVDD_CORE - Digital Core Power Supply
ï¼
DVDD_CORE ï¼
17 F3
DVDD_IO - Digital IO Power Supply
ï¼
DVDD_IO
ï¼
18 B3
DVSS
- Digital Ground
DVDD_IO,
ï¼
ï¼
DVDD_CORE
19 F2
CLKI
PLL Reference Clock Input
I
(19.2/19.68/19.8 MHz)
ï¼
DVDD_IO
D
20 B2
RSTB
I Reset Input L: Reset
ï¼
DVDD_IO
A
21 E1
CSB
CPU Interface Select Pin
I (L ï¼CPU I/F DVDD_IO ï¼ I2C I/F)
ï¼
DVDD_IO
B
22 C1
SCLK
I CPU Interface Clock
ï¼
DVDD_IO
A
23 D1
CPU Interface Data Input/Output
SIO
I/O
(at Reset Input)
Hi-Z
DVDD_IO
F
24 C2
CPU Interface Data Output
SO
I/O
(connected to DVSS when not in use)
Hi-Z
DVDD_IO
E
25 E5
SDI
I Audio DAC Digital Data Input
Hi-Z
DVDD_IO
C
26 F4
BCLK
I/O Audio DAC Bit Clock (Input State at Reset)
Hi-Z
DVDD_IO
E
27 F5
LRCLK I/O Audio DAC LR Clock (Input State at Reset)
Hi-Z
DVDD_IO
E
28 D2
MCLK
I/O Audio DAC Master Clock (Input State at reset )
Hi-Z
DVDD_IO
E
Test Pin (connected to DVSS during normal
29 F6
TEST1
I
Pull-down DVDD_IO
C
operation)
Test Pin (connected to DVSS during normal
30 F1
TEST2
I
Pull-down DVDD_IO
C
operation)
31 A1
TEST3 I/O Test Pin (released during normal operation)
ï¼
DVDD_IO
E
32 A6
TEST4
I Test Pin (released during normal operation)
ï¼
AVDD
ï¼
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