BU7839GVW Datasheet, PDF (9/16 Pages) Rohm – Digital Input Hi-Fi Class-D Headphone Amplifier

● Acknowledge
After START condition is generated, data is transmitted at 8 bits once. After 8 bit transmission, the transmitter
opens SDA, and the receiver returns the acknowledge signal with SDA taken as L.
SD_トA o_ラut_ンpu_スt b_ミy t_ッra_タnsm_にit_よter_る
SDA 出力
SDA outpu_レt b_シy _ーrec_バei_にve_よr _る
SDA 出力
SCL
1
S
S_STA_TR_AT_RTCO_条N_件DITION
Non-acknowledge
非アクノリッジ
acknow_アle_クdg_ノe _{リッジ}
2
8
9
アCクlocノk pリuッlseジfo用r
ク^aロ^ckッ^noク^wパ^ledル^geス
● Write protocol
Write protocol is shown below. Register address is transmitted by 1 byte after device address and write command
have been transmitted. Third byte writes the data, which is written in by second byte, into internal register, and for
fourth byte and subsequent bytes, the register address is incremented automatically. But, the register address
becomes 00h by the transmission of 1 byte after the register address has become the final address (6Ch). The
address is incremented after the transmission is over.
S 0 1 1 0 0 1 1 0 A A7 A6 A5 A4 A3 A2 A1 A0 A D7 D6 D5 D4 D3 D2 D1 D0 A
D7 D6 D5 D4 D3 D2 D1 D0 A P
Devデicバeイaスdアdドrレeスss
Reレgジisスteタrアaドdレdスress
R/W=0(書(きW込rみite) in)
T_マran_スsm_タit_ーting_側se_がt is_送on_ä¿¡M_è£ast_ç½®er side
Tr_スan_レsm_ーitti_ブng_側se_がt is_送on_ä¿¡Sla_è£ve_ç½®side
Data データ
Re_レg_ジis_スte_タr_アa_ドd_レd_スress
インiクnリcrメeンmトent
A=Aアcクknノoリwッleジdge
A=N非oアn-クaノckリnッoジwledge
S=SスTタAーRTトコcoンnデditィioシn ョン
P=SスTトOッPプcコonンdデitioィnション
Sr=R再et送ra開ns始m条iss件ion starting condition
デDーaタta
Regレisジtスerタアadドdレrスess
イン_inク_cリ_reメ_mン_eト_nt
● Readout protocol
Readout starts from 1 byte after device address and R/W bit have been written in. For the address after the readout
register is finally accessed and the subsequent addresses, the data of the addresses that have been incremented is
read out. As the readout of 1 byte after the address has become the final address, 00h is read out. The address is
incremented after the transmission is over.
S 0 1 1 0 0 1 1 0 A D7 D6 D5 D4 D3 D2 D1 D0 A
Deデviバceイスadアdドrレesスs
R/W=0(書(きW込riみte) in)
Dデaーtaタ
Rレeジgiスstタeアr ドadレdスress
インク_inリ_cメ_reン_mト_ent
D7 D6 D5 D4 D3 D2 D1 D0 A P
デーDタata
Rレegジisスtタerアaドdレdスress
インク_inリ_crメ_eン_mト_ent
Tr_マans_スmi_タttin_ーg s_側et i_がs on_送M_ä¿¡ast_è£er s_ç½®ide
T_スran_レsm_ーitti_ブng _側set_がis o_送n S_ä¿¡lav_è£e _ç½®side
A=ア_Acク_knノ_oリ_wッ_leジ_dge
A=非Noアn-クacノkリnoッwジledge
S=スSTタAーRTトcコonンdデitioィnション
P=ス^STト^Oッ^Pプ^coコⁿン^ditデ^ionィション
Sr=^R再^et送^ran開^sm始^is条^si件^{on starting condition}
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