BU7839GVW Datasheet, PDF (10/16 Pages) Rohm – Digital Input Hi-Fi Class-D Headphone Amplifier

● Compound readout protocol
After internal address is specified, create the retransmission starting condition, change the data transmitting
direction and implement the readout. Subsequently, the data of the address that has been incremented is read out. As
the readout of 1 byte after the address has become the final address, 00h is read out. The address is incremented
after the transmission is over. After retransmission starting condition, compound write is possible with R/W=0 (write in).
S 0 1 1 0 0 1 1 0 A A7 A6 A5 A4 A3 A2 A1 A0 A Sr 0 1 1 0 0 1 1 1 A
Device address
R/W=(0W(Writheiteinin) )
Register address
Slave address
R/ W= 1^(Re^ea^ad^do^ou^ut^t)⁾
D7 D6 D5 D4 D3 D2 D1 D0 A
D7 D6 D5 D4 D3 D2 D1 D0 A P
Data
Data
Register address
increment
Transmitting set is on Master side
Transmitting set is on slave side
A=アAcクknノoリwッleジdge
A=非Noアn-クacノkリnoッwジledge
S=ス^STタ^Aー^Rト^Tコ^coンⁿデ^ditィ^ioシⁿ ョ ン
P=ス^STト^Oッ^Pプ^cコ^onン^dデ^itioィⁿショ ン
Sr=^R再^e送^tra開^ns始^mi条^ss件^{ion starting condition}
Register address
increment
● Timing diagram
（反復）
(SRT_SeAp_TReTAatec_Rdo)_{Tnd条itio件n}
BIT 7
BIT 6
tSU;STA tLOW tHIGH 1/fSCLK
アクノ
Ack_リno_ッwle_ジdge
SSTTOOP Pcon条diti件on
SCL
SDA
t BUF t HD;STA
tSU;DAT t HD;DAT
tSU;STO
Ta=25 degree,DVDD=DVDDIO=1.8V, VDD_R=VDD_L=PLLVDD=3.0V
Standard
Item
Symbol
mode
min max
High-speed
mode
min max
SCL clock frequency
fSCLK
0
100
0
400
Hold time of START condition
ｔ_HD;STA
4.0
-
0.6
-
"Ｌ" Level time of SCL
ｔ_{ＬＯＷ}
4.7
-
1.3
-
"H" Level time of SCL
ｔ_{ＨＩＧＨ}
4.0
-
0.6
-
Setup time of repeated START condition
ｔ_{ＳＵ;STA}
4.7
-
0.6
-
Data hold time 1
t_HD;DAT
0.1 3.45 0.1
0.9
Data setup time
t_SU;DAT
250
-
100
-
Setup time of STOP condition
t_SU;STO
4.0
-
0.6
-
Bus opening time between STOP condition and START
condition
t_BUF
4.7
-
1.3
-
*1 The maximum tHD;DAT is not allowed to exceed the “L” level time （tLOW） of SCL signal
Unit
kHz
μs
μs
μs
μs
μs
ns
μs
μs
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