BU4015B_09 Datasheet, PDF (9/18 Pages) Rohm – High Voltage CMOS Logic ICs

BU4015B,BU4015BF,BU4021B,BU4021BF,
BU4094BC,BU4094BCF,BU4094BCFV,BU4538B,BU4028B
Technical Note
●Electrical Characteristics Curves(BU4021B)
50
50
[BU4021B/F]
40
VDD=15[V]
30
-40[℃]
25[℃]
85[℃]
20
VDD=10[V]
-40[℃]
25[℃]
10 -40[℃]
85[℃]
25[℃]
85[℃]
0
VDD=5[V]
0
5
10
15
20
Output Voltage [V]
Fig.11 Output source
current－voltage
800
[BU4021B/F]
700
600
VDD=3[V]
40
30
20
10
0
0
800
700
600
[BU4021B/F]
VDD=15[V]
-40[℃]
25[℃]
85[℃]
-40[℃]
25[℃] VDD=10[V]
85[℃]
-40[℃]
25[℃] VDD=5[V]
85[℃]
5
10
15
20
Output Voltage [V]
Fig.12 Output sink
current－voltage
[BU4021B/F]
VDD=3[V]
800
[BU4021B/F]
700
600
VDD=3[V]
500
Operating Temperature Range
400
VDD=5[V]
300
200
VDD=10[V]
100
VDD=16[V]
0
-50 -25 0
25 50 75 100
Ambient Temperature [℃]
Fig.13 Propagation delay tPLH
CLK→QS
800
[BU4021B/F]
700
600
VDD=3[V]
500
Operating Temperature Range
400
VDD=5[V]
300
500
Operating Temperature Range
400
VDD=5[V]
300
500
Operating Temperature Range
400
VDD=5[V]
300
200
VDD=10[V]
100
VDD=16[V]
0
-50 -25 0
25 50 75 100
Ambient Temperature [℃]
Fig.14 Propagation delay tPHL
CLK→QS
200
[BU4021B/F]
175
Operating Temperature Range
150
125
VDD=3[V]
100
75
50
25
0
-50
VDD=5[V]
VDD=10[V]
VDD=16[V]
-25 0 25 50 75 100
Ambient Temperature [℃]
Fig.17 Set up time tsu
Q→CLK
200
180
160
140
120
100
80
60
40
20
0
-50
[BU4021B/F]
Operating Temperature Range
VDD=3[V]
VDD=5[V]
VDD=10[V]
VDD=16[V]
-25 0 25 50 75 100
Ambient Temperature [℃]
Fig.20 Minimum P/S
pulse width
200
VDD=10[V]
100
VDD=16[V]
0
-50 -25 0
25 50 75 100
Ambient Temperature [℃]
Fig.15 Propagation delay tPLH
P/S→QS
200
[BU4021B/F]
180
160
Operating Temperature Range
140
VDD=3[V]
120
100
80
VDD=5[V]
60
40
VDD=10[V]
20
VDD=16[V]
0
-50 -25 0
25 50 75 100
Ambient Temperature [℃]
Fig.18 Hold time th
CLK→Q
○Switching characteristics
200
VDD=10[V]
100
VDD=16[V]
0
-50 -25 0
25 50 75 100
Ambient Temperature [℃]
Fig.16 Propagation delay tPHL
P/S→QS
200
[BU4021B/F]
180
160
VDD=3[V]
140
120
Operating Temperature Range
100
80
VDD=5[V]
60
VDD=10[V]
40
VDD=16[V]
20
0
-50 -25 0 25 50 75 100
Ambient Temperature [℃]
Fig.19 Minimum CLK
pulse width
20[ns]
20[ns]
Parallel Data
or
Serial Data
CLOCK
or
P/S
90%
50%
10%
tsu
10%
tW
90%
50%
tr
tf
th
OUTPUT
tPLH _90%
50%
10%
tPHL
tTLH
tTHL
VDD
GND(VSS)
VDD
GND(VSS)
VOH
VOL
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9/17
2009.06 - Rev.A