BU4015B_09 Datasheet, PDF (12/18 Pages) Rohm – High Voltage CMOS Logic ICs

BU4015B,BU4015BF,BU4021B,BU4021BF,
BU4094BC,BU4094BCF,BU4094BCFV,BU4538B,BU4028B
●Reference data(BU4028B)
50
[BU4028B]
40
30
VDD=15[V]
-40[℃]
25[℃]
20
85[℃]
VDD=10[V]
10
-40[℃]
-40[℃] _25[℃]
25[℃]
85[℃]
85[℃]
0
VDD=5[V]
0
5
10
15
20
Output Voltage [V]
Fig.40 Output source
current－voltage
400
[BU4028B]
350
VDD=3[V]
300
250
200
Operating Temperature Range
VDD=5[V]
150
100
VDD=10[V]
50
VDD=16[V]
0
-50 -25 0 25 50 75 100
Ambient Temperature [℃]
Fig.43 Propagation delay tTHL
(*) Switching characteristics is shown in P15.
50
40
30
20
10
0
0
500
400
[BU4028B]
VDD=15[V]
-40[℃]
25[℃]
85[℃]
-40[℃]
25[℃] VDD=10[V]
85[℃]
-40[℃]
25[℃] VDD=5[V]
85[℃]
5
10
15
20
Output Voltage [V]
Fig.41 Output sink
current－voltage
[BU4028B]
VDD=3[V]
300
Operating Temperature Range
200
VDD=5[V]
VDD=10[V]
100
VDD=16[V]
0
-50 -25 0
25 50 75 100
Ambient Temperature [℃]
Fig.44 Propagation delay tPLH
Technical Note
400
[BU4028B]
350
300
VDD=3[V]
250
VDD=5[V]
200
150
VDD=10[V]
100
VDD=16[V]
50
Operating Voltage Range
0
-50 -25 0 25 50 75 100
Ambient Temperature [℃]
Fig.42 Propagation delay tTLH
500
[BU4028B]
400
VDD=3[V]
300
Operating Temperature Range
200
VDD=5[V]
VDD=10[V]
100
VDD=16[V]
0
-50 -25 0
25 50 75 100
Ambient Temperature [℃]
Fig.45 Propagation delay tPHL
●Description of BU4015B series model
Function：Dual 4-bit static shift register
1) Description of operation
Dual 4-bit static shift register of BU4015B is configured with 2 independent serial input/parallel output registers of the same 4-state.
Each register is provided with an independent clock and reset input having one series data input. Register state is the D
type master/slave flip-flop. Data is shifted to the next stage during the rise time of the clock. Each register can be cleared
by addition of “H” level to reset.
PIN arrangement
CLOCK B ¹
Q3B ²
Q2B ³
Q1A ⁴
Q0A ⁵
RESET A ⁶
DA ⁷
VSS ⁸
CL R D
Q3 Q2 Q1 Q0
Q0 Q1 Q2 Q3
CL R D
Block diagram
16 _VDD
15 _D8
D
14 _{RESET B}
13 _Q0B
12 _Q1B
11 _Q2B
CLOCK
RESET
10 _Q3A
9 _{CLOCK A}
Q0
Q1
Q2
Q3
DQ
CL Q
R
DQ
CL Q
R
DQ
CL Q
R
DQ
CL Q
R
Truth table
CLOCK
X
X：Don't Care
D RESET Q0 Q1 Q2 Q3
L
L
L Q0 Q1 Q2
H
L
H Q0 Q1 Q2
X
L
L
No Change
X
H
LLLL
PIN description
PIN No. Symbol I/O
1 CLOCKB I
2
Q3B O
3
Q2A O
4
Q1A O
5
Q0A O
6 RESETA I
7
DA
I
8
VSS ―
9 CLOCKA I
10
Q3A O
11
Q2B O
12
Q1B O
13
Q0B O
14 RESETB I
15
DB
I
16
VDD ―
Function
Clock input (CHB)
Output 3 (CHB)
Output 2 (CHA)
Output 1 (CHB)
Output 0 (CHA)
Reset input (CHA)
Data input (CHA)
Power supply(-)
Clock input (CHA)
Output 3 (CHA)
Output 2 (CHB)
Output 1 (CHB)
Output 0 (CHB)
Reset input (CHB)
Data input (CHB)
Power supply(+)
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12/17
2009.06 - Rev.A