BU1S12S1AG-LB Datasheet, PDF (9/20 Pages) Rohm – Successive Approximation A/D Converter

BU1S12S1AG-LB
Description of Functions
1. Overview of A/D Conversion Process
BU1S12S1AG-LB is a successive-approximation A/D converter designed with a charge-redistribution D/A converter.
Simplified schematics of the A/D converter are shown in Figure 18 and Figure 19.
Figure 18 shows the A/D converter in Track mode: the switch SW1 is in the position A, SW2 is closed and balances the
comparator. Then, the sampling capacitor is charged with the analog input voltage VIN.
Figure 19 shows the A/D converter in Hold mode. When a conversion starts, the A/D converter goes into Hold mode:
SW2 becomes open, SW1 connects the sampling capacitor to ground through the terminal B and the comparator loses
its balance. The control logic controls the input voltage of the comparator via the sampling capacitors of the
charge-redistribution D/A converter to get the comparator back into a balanced state. A/D conversion finishes when the
comparator balances again. The control logic also generates the output code of the A/D converter.
VIN
A
SW1
B
SAMPLING
CAPACITOR
SW2
GND
VA
2
CHARGE
REDISTRIBUTION
DAC
CONTROL
LOGIC
Figure 18. Track mode
VIN
A
SW1
B
SAMPLING
CAPACITOR
SW2
GND
VA
2
CHARGE
REDISTRIBUTION
DAC
CONTROL
LOGIC
Figure 19. Hold mode
2. Ideal Transfer Characteristics
Figure 20 shows the ideal transfer characteristics of BU1S12S1AG-LB. Code transitions occur midway between
successive integer LSB values, such as 0.5 LSB, 1.5 LSB, and so on. The LSB size for the BU1S12S1AG-LB is VA /
4096. The output code format of the A/D converter is straight binary
111...111
111...110
111...000
011...111
1LSB = VA / 4096
000...010
000...001
000...000
0.5LSB
0V
+VA - 1.5 LSB
ANALOG INPUT
Figure 20. Ideal Transfer Characteristics
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TSZ22111・15・001
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TSZ02201-0GSG0GZ10180-1-2
04.Jul.2016 Rev.001