BU1S12S1AG-LB Datasheet, PDF (5/20 Pages) Rohm – Successive Approximation A/D Converter

BU1S12S1AG-LB
Timing Specifications
Unless otherwise specified, Ta=-40°C to +85°C (Typical: Ta=25°C), VA=2.7 to 5.25V, fSCLK=10 to 20MHz, CL=25pF
Parameter
Conversion Time
CSB Pulse Width
CSB Setup Time
SDATA Enable Time
SDATA Access Time 1
SDATA Access Time 2
SCLK Low Pulse Width
SCLK High Pulse Width
SDATA Hold Time 1
SDATA Hold Time 2
SDATA Disable Time 1
SDATA Disable Time 2
CSB Hold Time
SCLK Setup Time
Quiet Time
Power-Up Time
Throughput Period
Symbol
tCONV
t1
t2
t3
t4
t4
t5
t6
t7
t7
t8
t8
t9
t10
tQUIET
tPOWUP
tTHROUGHPUT
Min
-
10
10
-
-
-
0.4 x tSCLK
0.4 x tSCLK
7
5
6
5
10
10
50
-
1
Limits
Typ
16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
-
Max
Unit
Condition
-
SCLK
-
ns
-
ns
20
ns
40
ns
VA=2.7 to 3.6V
20
ns
VA=4.75 to 5.25V
-
ns
-
ns
-
ns
VA=2.7 to 3.6V
-
ns
VA=4.75 to 5.25V
25
ns
VA=2.7 to 3.6V
25
ns
VA=4.75 to 5.25V
-
ns
-
ns
-
ns
-
µs
20
µs
Hold mode
Track mode
CSB
SCLK
t9
tCONV
t2
t6
1
2
3
4
5
t10
13
14
15
16
t3
t4
t7
t5
t8
SDATA
ZERO ZERO ZERO ZERO DB11 DB10
High-Z
4 LEADING ZEROS
DB2 DB1 DB0
tTHROUGHPUT
t1
tQUIET
High-Z
(a) If SCLK is high at the falling edge of CSB
Hold mode
Track mode
CSB
SCLK
t9
tCONV
t2
t6
1
2
3
4
5
t10
13
14
15
16
t3
t4
t7
t5
t8
SDATA
High-Z
ZERO ZERO ZERO ZERO DB11 DB10
4 LEADING ZEROS
DB2 DB1 DB0
tTHROUGHPUT
t1
tQUIET
High-Z
(b) If SCLK is low at the falling edge of CSB
Figure 5. Serial Interface Timing Chart
(Note 1) When the BU1S12S1AG-LB is used at the sampling frequency of 1MSPS, it is recommended to hold SCLK
high at the falling edge of CSB as shown in Figure 5(a). (See also “3. Serial Interface” on page 10.)
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TSZ02201-0GSG0GZ10180-1-2
04.Jul.2016 Rev.001