BU1S12S1AG-LB Datasheet, PDF (11/20 Pages) Rohm – Successive Approximation A/D Converter

BU1S12S1AG-LB
4. Dummy Conversion
Dummy conversions are necessary in the following cases.
(1) A/D conversion after power-up
The first A/D conversion data after applying power to the BU1S12S1AG-LB is invalid. Therefore, a dummy
conversion is necessary after power-up before getting valid data. In addition, the power-up time is satisfied with a
cycle of the dummy conversion.
after power-up
CSB
dummy conversion
1
16
1
16
SCLK
SDATA
INVALID DATA
VALID DATA
Figure 22. A/D conversion after power-up
(2) A/D conversion after a stop period more than the maximum throughput time
The BU1S12S1AG-LB may stop performing A/D conversion between some A/D conversion cycles. If the maximum
limit of the throughput period of 20μsec is violated, the first A/D conversion data after the resumption is not valid
similar to the case after power-up. Therefore, a dummy conversion cycle is necessary when A/D conversions are
resumed after a stop period longer than the limit and the results later than the dummy conversion can be used
validly.
CSB
1
SCLK
SDATA
more than max throughput time
16
dummy conversion
1
16
1
VALID DATA
INVALID DATA
Figure 23. A/D conversion after a long suspension
16
VALID DATA
5. Pin Information
(1) Analog Input Pin
The equivalent analog input circuit is shown in Figure 24. The diodes, D1 and D2, are placed for ESD protection. If
the analog input voltage is more than “VA + 0.3V”, or less than “GND – 0.3V”, these diodes are turned on and
forward current is generated. This current might cause malfunction or irreversible damage to BU1S12S1AG-LB.
The capacitance value of the C1 in Figure 24 is typically 4pF, derived from the package parasitic capacitance. The
R1 is the resistance of the track/hold switch, typically 500Ω. The C2 is the sampling capacitance of
BU1S12S1AG-LB, and the capacitance value is typically 24pF.
VA
D1
R1
VIN
C1 _D2
SW1
OPEN : HOLD MODE _C2
CLOSE : TRACK MODE
Figure 24. Analog Input Equivalent Circuit
(2) Digital Input and Output Pins
The equivalent digital input circuit is shown in Figure 25. Digital input pins, CSB and SCLK, don’t have any diodes
to VA. Thus, the maximum rating of “VA + 0.3V” is not applied to these digital input pins. Digital input voltage range
can vary from ground to 5.25V regardless of the supply voltage VA. This enables BU1S12S1AG-LB to be
interfaced with a wide range of logic levels, independent of the supply voltage VA.
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TSZ22111・15・001
11/16
TSZ02201-0GSG0GZ10180-1-2
04.Jul.2016 Rev.001