BU7963GUW Datasheet, PDF (8/20 Pages) Rohm – Data rate 1350Mbps RGB Interface

BU7963GUW
Technical Note
PCLK Polarity Selection
BU7963GUW controls PCLK input polarity by POL_PCLK setting. Table 8 shows PCLK input polarity.
Table 8. PCLK Polarity Selection
POL_PCLK
Parallel Data Capturing Polarity
‘L’
Capture parallel data at falling edge.
‘H’
(default)
Capture parallel data at rising edge.
PLL Bandwidth Selection
BU7963GUW controls the range of the CLK+ / CLK− input frequency (= PCLK output frequency) by the setting of the
data format (LS1, and LS0) of the high-speed data channel and the bandwidth setting of PLL_BW.
Table 9. PLL_BW Setting
CLK+ / CLK− Frequency Range [MHz]
LS1
LS0 PLL_BW
(PCLK Input Frequency)
Min
Max
‘L’
‘L’
‘L’
4
8
‘L’
‘L’
‘H’
7
15
‘L’
‘H’
‘L’
8
16
‘L’
‘H’
‘H’
14
30
‘H’
‘L’
‘L’
12
24
‘H’
‘L’
‘H’
21
45
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8/19
2010.04 - Rev.A