BU7963GUW Datasheet, PDF (6/20 Pages) Rohm – Data rate 1350Mbps RGB Interface

BU7963GUW
Parallel Data Interface
29-pin
Name Width Level I/O
Table 4. Parallel Data Interface
Functions
PCLK
1 CMOS I PCLK interface.
PD[26:0]
CKD
27 CMOS I Parallel data interface.
Output of PCLK detection result.
1 CMOS O ‘L’: clock stop.
‘H’: clock detect.
Control
Name
XSD
LS0
LS1
RVS
8-pin
Width
Level
1 CMOS
1
CMOS
1
1 CMOS
Table 5. Control
I/O
Functions
Shutdown pin.
I ‘L’: shutdown.
‘H’: normal operation.
Selection of the number of data channel and
the data format.
I
＊Refer to "Selection of the number of
MSDL3 channels".
＊Set the same number of data channel
between the TX device and the RX device.
Selection of MSDL3 pins assignment.
I ‘L’: Default matrix.
‘H’: Flipped matrix.
PLL_BW
1 CMOS I Selection of PLL bandwidth.
Selection of input clock polarity.
POL_PCLK 1 CMOS I ‘L’: sample parallel data at falling.
‘H’: sample parallel data at rising.
TEST0
TEST1
1
Test mode pin.
Pull
down
I
‘L’: normal mode.
‘H’: test mode.
1
Must be ‘L.’
Technical Note
Shutdown
Equivalent
Schematic
Input
A
Input
A
‘L’
C
Shutdown
Equivalent
Schematic
Input
A
Input
A
Input
A
Input
A
Input
A
B
Input
B
DVDD
DVDD
DVDD
A
B
C
D
Fig.4. Equivalent Schematics
MSVDD
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2010.04 - Rev.A