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BU9890GUL-W Datasheet, PDF (7/14 Pages) Rohm – Silicon Monolithic Integrated Circuit
◇SYNCHRONOUS DATA TIMING
SCL
SDA
(IN)
SDA
(OUT)
tHD:STA
tBUF
tR
tF
tHIGH
tSU:DAT
tLOW
tPD
tHD:DAT
tDH
7/13
SCL
SDA
tSU:STA
tHD:STA
tSU:STO
START BIT
Fig.-4 SYNCHRONOUS DATA TIMING
STOP BIT
○SDA data is latched into the chip at the rising edge of SCL clock.
○Output date toggles at the falling edge of SCL clock.
◇WRITE CYCLE TIMING
SCL
SDA
D0
ACK
WRITE DATA(n)
tWR
STOP CONDITION
START CONDITION
Fig.-5 WRITE CYCLE TIMING
REV. A