BU9408KS2_12 Datasheet, PDF (49/57 Pages) Rohm – 32bit Audio DSP with Built-in 4ch DAC and ASRC

BU9408KS2
Technical Note
8. Commands Transmitted after Reset Release
The following commands must be transmitted after reset release, including after power supply stand-up.
0．Turn power on.
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Wait approximately 1ms until oscillation is stable. (The time to stabilization should be adjusted according to the
pendulum product.)
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1. Reset release (RESETB = “H”), Mute release (MUTE1B,MUTE2B,MUTE3B = “H”)
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Wait approximately 500us until RAM initialization is complete.
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2. &hF1[2] = 0 : Signals from the analog block are connected to the digital block.
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3. &hF3[1] = 0 : CLK100M for a down sample block of ASRC is set as a normal mode. (&hF3 = 00h）
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4．&hB0[5:4] = 0 : Configure PLL clock to regular use state. (&hB0 = 02）
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5. &hB1[7:0] = AAh : The phase of the clock outputted from PLL is adjusted.
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6. &h03[5:4][1:0] = 0 : Select input at SP1 and SP2.
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7. &h18[7] = 0 : Set 1 when use SPDIF. (Needless set when not use SPDIF.)
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8. &hA0 = A6h : Configure PLLA1.
&hA1 = A0h
&hA2 = A4h
&hA3 = A4h
&hA4 = 00h
&hA7 = 40h
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9. &hA8 = A6h : Configure PLLA2.
&hA9 = A0h
&hAA = A4h
&hAB = A4h
&hAC = 00h
&hAF = 40h
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Wait approximately 20ms until PLL is stable.
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10. &h01[7:6] = 0 : The data clear of built-in RAM is completed and it changes into the condition
that RAM can be used.
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11. &h08[4][0] = 0 : Configure system clock..
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12. &h14 = C0h : The data clear of ASRC is completed and it changes into normal condition.
&h14 = 40h
&h14 = 01h
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13. Configuration of other registers.
&h26[7:0] = **h : Mute release of Main data output volume （30h = 0dB）
&h2C[7:0] = **h : Mute release of Sub data output volume (30h = 0dB)
&h92[7:0] = **h : Mute release of DF1+ΔΣDAC output volume （0Ch = 0dB）
&h95[7:0] = **h : Mute release of DF2+16bitDACoutput volume （0Ch = 0dB）
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2012.03 - Rev.A