BU9408KS2_12 Datasheet, PDF (12/57 Pages) Rohm – 32bit Audio DSP with Built-in 4ch DAC and ASRC

BU9408KS2
Technical Note
2-8. Output data selecting DF2＋16bitDAC (SEL4)
Default = 0
Select Address
&h06 [ 6:4 ]
Value
0
1
2
3
4
Operation Description
Output data from S-P conversion 1 (Refer to &h03 [5:4])
Output data from S-P conversion 2 (Refer to &h03 [1:0])
Data output before DSP operation
Main data output after DSP operation
Sub data output after DSP operation
2-9. Output clock selecting AMCLKO terminal (SEL8)
Default = 0
Select Address
&h07 [ 3:0 ]
Value
0
1
2
3
4
5
6
7
8
Operation Description
Output the 256fs (12.288MHz) clock of an input from the XI terminal.
Output the 256fs clock made from PLL1
Output the 256fs clock made from PLL2
Output the 512fs (24.576MHz) clock of an input from the XI terminal.
Output the 512fs clock made from PLL1
Output the 512fs clock made from PLL2
Output the 128fs (6.144MHz) clock of an input from the XI terminal.
Output the 128fs clock made from PLL1
Output the 128fs clock made from PLL2
There are three system clocks used by ASRC of BU9408KS2, DSP, the P-S conversion 1, the P-S conversion 2, a SPDIF
output part, DF1+sigma-delta DAC, and DF2+16bit DAC.
One is a 24.576MHz (512fs) system clock from XI terminal, and other two are a clock of 512fs made from PLL1 or PLL2.
2-10. System Clock Selecting of Input Part of ASRC (it is Used for up sampling) (Dotted line ①)
Default = 0
Select Address
&h08 [ 0 ]
Value
0
1
Operation Description
The 24.576MHz (512fs) system clock from the XI terminal
The clock of 512fs made from PLL1 of the S-P conversion 1
2-11. The output part of ASRC (it is used for down sampling), DSP, P-S conversion 1, system clock selecting of a SPDIF output
part (Dotted line ②)
Default = 0
Select Address
&h08 [ 4 ]
Value
0
1
Operation Description
The 24.576MHz (512fs) system clock from the XI terminal
The clock of 512fs made from PLL1 of the S-P conversion 1
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2012.03 - Rev.A