BU7411G Datasheet, PDF (4/5 Pages) Rohm – SILICON MONOLITHIC INTEGRATED CIRCUIT

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(6) Output short circuit
If short circuit occurs between the output terminal and VDD terminal, excessive
in output current may flow and generate heat, causing destruction of the IC. Take due care.
(7) Using under strong electromagnetic field
Be careful when using the IC under strong electromagnetic field because it may malfunction.
(8) Usage of IC
When stress is applied to the IC through warp of the printed circuit board,
The characteristics may fluctuate due to the piezo effect.
Be careful of the warp of the printed circuit board.
(9) Testing IC on the set board
When testing IC on the set board, in cases where the capacitor is connected to the low impedance,
make sure to discharge per fabrication because there is a possibility that IC may be damaged by stress.
When removing IC from the set board, it is essential to cut supply voltage.
As a countermeasure against the static electricity, observe proper grounding during fabrication process
and take due care when carrying and storage it.
(10) The IC destruction caused by capacitive load
The transistors in circuits may be damaged when VDD terminal and VSS terminal is shorted with the charged
output terminal capacitor.
When IC is used as a operational amplifier or as an application circuit, where oscillation is not activated
by an output capacitor,the output capacitor must be kept below 0.1[μF] in order to prevent the damage
mentioned above.
(11) Decupling capacitor
Insert the decupling capacitance between VDD and VSS, for stable operation of operational amplifier.
(12) Latch up
Be careful of input voltage that exceed the VDD and VSS. When CMOS device have sometimes occur
latch up operation. And protect the IC from abnormaly noise
(13) Crossorver distortion
Inverting amplifier is generete crossover distortion when feed back resistance value is small.
To supress the crosover distortion, connect a resistor between the output terminal and VSS
Then increse the bias current to enable class A output stage operation.
Feed back resistance
VDD
-
+
Pull down resistance
VSS
Fig1.Pull down resistance
REV. D